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Wed, 11 Nov 2026 05:39:32 -0800 (PST) Received: from dev.Default ([86.127.229.203]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4ba01fea745sm136757365e9.10.2026.11.11.05.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 05:39:32 -0800 (PST) From: Agustin Santiago Isasmendi To: Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Arnd Bergmann , =?UTF-8?q?Stefan=20D=C3=B6singer?= , Navid Ghahremani , Krzysztof Kozlowski Subject: [PATCH 0/2] ARM: l2c: honour status = "disabled" on the L2 cache node Date: Wed, 11 Nov 2026 14:39:28 +0100 Message-Id: <20261111133930.3665251-1-isasmendi.agus@gmail.com> X-Mailer: git-send-email 2.30.2 X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261111_053935_189737_733650AC X-CRM114-Status: GOOD ( 13.52 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Russell, l2x0_of_init() finds the L2 cache node by compatible and never looks at its status property, so a device tree cannot keep the L2 cache off. Patch 2 makes it honour status = "disabled", as the newer cache controller drivers in drivers/cache/ already do. If the firmware left the cache enabled it cannot just be ignored, since nothing would maintain it, so it is cleaned, invalidated and disabled instead. Patch 1 moves the number-of-ways computation out of the per-part init code so that the disable path can reuse it. The user is the ZTE ZX279128S (dual Cortex-A9, L2C-310 r3p3), where a PCIe read on one CPU deadlocks against an L2C-310 line operation by physical address or a Cache Sync on the other CPU, and the board hangs within seconds of WiFi traffic. Running with the L2 cache off avoids it, and that was suggested as the fallback for the platform when a lock-based workaround was found too invasive for generic code: https://lore.kernel.org/r/20261110153522.1620088-1-isasmendi.agus@gmail.com Whether the ZX279128S device tree disables the cache is a decision for that thread; this series only makes the property work. No in-tree L2 cache node is disabled, so existing device trees are not affected. Tested on the ZTE ZXHN H3600 (not in mainline yet, on top of Navid Ghahremani's v2 platform series): with the node disabled the cache stays off (control register 0) and the system runs normally; with it enabled the cache comes up as before; the firmware-enabled path was exercised with a test-only change that enables the cache before the check. Builds without warnings with W=1 (board config and multi_v7_defconfig); checkpatch --strict is clean. Agustin Santiago Isasmendi (2): ARM: l2c: factor out the number of ways ARM: l2c: honour status = "disabled" on the L2 cache node arch/arm/mm/cache-l2x0.c | 85 ++++++++++++++++++++++++++++------------ 1 file changed, 59 insertions(+), 26 deletions(-) base-commit: c03c1a14507dfaf8b856c2608f9ac216021fc222 -- 2.30.2