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Wed, 11 Nov 2026 23:29:58 -0800 (PST) Received: from dev.Default ([86.127.229.203]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4ba0951bf2asm81897575e9.4.2026.11.11.23.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 23:29:56 -0800 (PST) From: Agustin Santiago Isasmendi To: Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Arnd Bergmann , =?UTF-8?q?Stefan=20D=C3=B6singer?= , Navid Ghahremani , Krzysztof Kozlowski , Rob Herring , Conor Dooley , devicetree@vger.kernel.org Subject: [PATCH v2 2/2] ARM: l2c: honour status = "disabled" on the L2 cache node Date: Thu, 12 Nov 2026 08:29:53 +0100 Message-Id: <20261112072953.989664-3-isasmendi.agus@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20261112072953.989664-1-isasmendi.agus@gmail.com> References: <20261112072953.989664-1-isasmendi.agus@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261111_233001_272116_80F1C971 X-CRM114-Status: GOOD ( 15.97 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 l2x0_of_init() looks the L2 cache node up by compatible and enables the cache whatever its status property says, so a device tree cannot keep the L2 cache off. On the ZTE ZX279128S (dual Cortex-A9, L2C-310 r3p3) a PCIe read on one CPU deadlocks against an L2C-310 line operation by physical address or a Cache Sync on the other CPU, and the board hangs within seconds of WiFi traffic. Running with the L2 cache off avoids the deadlock, so a board needs a way to say so. Honour the status property, as the newer cache controller drivers already do (drivers/cache/ax45mp_cache.c, starfive_starlink_cache.c): leave a disabled node alone. The firmware is responsible for leaving the cache disabled in that case; the kernel does not check. No in-tree L2 cache node is disabled, so nothing changes for existing device trees. Tested on the ZTE ZXHN H3600: with the node disabled the cache stays off and the system runs normally; with it enabled the cache comes up as before. Assisted-by: LLM Reviewed-by: Arnd Bergmann Signed-off-by: Agustin Santiago Isasmendi --- arch/arm/mm/cache-l2x0.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 470867160076..5d6a4c040a50 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1772,6 +1772,11 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) if (!np) return -ENODEV; + if (!of_device_is_available(np)) { + pr_info("L2C: disabled by the device tree\n"); + return -ENODEV; + } + if (of_address_to_resource(np, 0, &res)) return -ENODEV; -- 2.30.2