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Thu, 12 Nov 2026 22:52:57 -0800 (PST) Received: from a1-free ([161.33.196.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b1b3d279d8sm869257a91.2.2026.11.12.22.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 22:52:57 -0800 (PST) From: TAKANO Mitsuhiro To: linux-perf-users@vger.kernel.org, Arnaldo Carvalho de Melo , Namhyung Kim Cc: James Clark , Ian Rogers , John Garry , Ilkka Koskinen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, TAKANO Mitsuhiro Subject: [PATCH v2] perf vendor events arm64 AmpereOneX: Fix misspelled PublicDescription keys Date: Fri, 13 Nov 2026 06:52:53 +0000 Message-ID: <20261113065253.746615-1-takano32@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261108183846.3804875-1-takano32@gmail.com> References: <20261108183846.3804875-1-takano32@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261112_225258_965151_54148D96 X-CRM114-Status: GOOD ( 13.65 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Sixteen of the 28 entries in mmu.json spell PublicDescription as "PublicDescrition"; the other 12 spell it correctly. jevents.py reads only the keys it asks for by name, so those 16 fields are dead. Fixing them does not change the perf list output: every one of the 16 entries has a BriefDescription with the same text, and jevents.py drops the long description when it equals the brief one (jevents.py:405). Running jevents.py for arm64 before and after this change gives a byte-identical generated string table (1580383 bytes both times). The file becomes self-consistent again, and the field works if the brief text is ever changed on its own. No text, name, code or expression changes. Written with Hermes Agent, an LLM assistant; the author reviewed it and ran the generator as described. perf was built, not run against hardware. Signed-off-by: TAKANO Mitsuhiro --- v2: rebased on 7.4-rc2. The arm64 string table generated with jevents.py is byte identical before and after the change (1580383 bytes), measured again on this base. .../arch/arm64/ampere/ampereonex/mmu.json | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json index 66d83b680651..9457f9be4ecc 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json @@ -30,37 +30,37 @@ "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry" }, { - "PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry", + "PublicDescription": "Data TLB translation cache hit on S2L1 walk cache entry", "EventCode": "0xd805", "EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK", "BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry" }, { - "PublicDescrition": "Data TLB translation cache hit on S2L0 walk cache entry", + "PublicDescription": "Data TLB translation cache hit on S2L0 walk cache entry", "EventCode": "0xd806", "EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK", "BriefDescription": "Data TLB translation cache hit on S2L0 walk cache entry" }, { - "PublicDescrition": "Data-side S1 page walk cache lookup", + "PublicDescription": "Data-side S1 page walk cache lookup", "EventCode": "0xd807", "EventName": "MMU_D_S1_WALK_CACHE_LOOKUP", "BriefDescription": "Data-side S1 page walk cache lookup" }, { - "PublicDescrition": "Data-side S1 page walk cache refill", + "PublicDescription": "Data-side S1 page walk cache refill", "EventCode": "0xd808", "EventName": "MMU_D_S1_WALK_CACHE_REFILL", "BriefDescription": "Data-side S1 page walk cache refill" }, { - "PublicDescrition": "Data-side S2 page walk cache lookup", + "PublicDescription": "Data-side S2 page walk cache lookup", "EventCode": "0xd809", "EventName": "MMU_D_S2_WALK_CACHE_LOOKUP", "BriefDescription": "Data-side S2 page walk cache lookup" }, { - "PublicDescrition": "Data-side S2 page walk cache refill", + "PublicDescription": "Data-side S2 page walk cache refill", "EventCode": "0xd80a", "EventName": "MMU_D_S2_WALK_CACHE_REFILL", "BriefDescription": "Data-side S2 page walk cache refill" @@ -90,61 +90,61 @@ "BriefDescription": "Level 2 instruction translation buffer allocation" }, { - "PublicDescrition": "Instruction TLB translation cache hit on S1L2 walk cache entry", + "PublicDescription": "Instruction TLB translation cache hit on S1L2 walk cache entry", "EventCode": "0xd901", "EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK", "BriefDescription": "Instruction TLB translation cache hit on S1L2 walk cache entry" }, { - "PublicDescrition": "Instruction TLB translation cache hit on S1L1 walk cache entry", + "PublicDescription": "Instruction TLB translation cache hit on S1L1 walk cache entry", "EventCode": "0xd902", "EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK", "BriefDescription": "Instruction TLB translation cache hit on S1L1 walk cache entry" }, { - "PublicDescrition": "Instruction TLB translation cache hit on S1L0 walk cache entry", + "PublicDescription": "Instruction TLB translation cache hit on S1L0 walk cache entry", "EventCode": "0xd903", "EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK", "BriefDescription": "Instruction TLB translation cache hit on S1L0 walk cache entry" }, { - "PublicDescrition": "Instruction TLB translation cache hit on S2L2 walk cache entry", + "PublicDescription": "Instruction TLB translation cache hit on S2L2 walk cache entry", "EventCode": "0xd904", "EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK", "BriefDescription": "Instruction TLB translation cache hit on S2L2 walk cache entry" }, { - "PublicDescrition": "Instruction TLB translation cache hit on S2L1 walk cache entry", + "PublicDescription": "Instruction TLB translation cache hit on S2L1 walk cache entry", "EventCode": "0xd905", "EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK", "BriefDescription": "Instruction TLB translation cache hit on S2L1 walk cache entry" }, { - "PublicDescrition": "Instruction TLB translation cache hit on S2L0 walk cache entry", + "PublicDescription": "Instruction TLB translation cache hit on S2L0 walk cache entry", "EventCode": "0xd906", "EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK", "BriefDescription": "Instruction TLB translation cache hit on S2L0 walk cache entry" }, { - "PublicDescrition": "Instruction-side S1 page walk cache lookup", + "PublicDescription": "Instruction-side S1 page walk cache lookup", "EventCode": "0xd907", "EventName": "MMU_I_S1_WALK_CACHE_LOOKUP", "BriefDescription": "Instruction-side S1 page walk cache lookup" }, { - "PublicDescrition": "Instruction-side S1 page walk cache refill", + "PublicDescription": "Instruction-side S1 page walk cache refill", "EventCode": "0xd908", "EventName": "MMU_I_S1_WALK_CACHE_REFILL", "BriefDescription": "Instruction-side S1 page walk cache refill" }, { - "PublicDescrition": "Instruction-side S2 page walk cache lookup", + "PublicDescription": "Instruction-side S2 page walk cache lookup", "EventCode": "0xd909", "EventName": "MMU_I_S2_WALK_CACHE_LOOKUP", "BriefDescription": "Instruction-side S2 page walk cache lookup" }, { - "PublicDescrition": "Instruction-side S2 page walk cache refill", + "PublicDescription": "Instruction-side S2 page walk cache refill", "EventCode": "0xd90a", "EventName": "MMU_I_S2_WALK_CACHE_REFILL", "BriefDescription": "Instruction-side S2 page walk cache refill" base-commit: 7475ea8b58616b33c04afb976cf0fbaad9dd63fb -- 2.53.0