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Sat, 14 Nov 2026 00:13:50 +0000 (UTC) From: Arun Iyengar via B4 Relay Date: Sat, 14 Nov 2026 00:13:50 +0000 Subject: [PATCH 1/3] media: dt-bindings: Add Rockchip IEP2 deinterlacer X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-Id: <20261114-iep2-v1-1-a8edde5a21e1@gmail.com> References: <20261114-iep2-v1-0-a8edde5a21e1@gmail.com> In-Reply-To: <20261114-iep2-v1-0-a8edde5a21e1@gmail.com> To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Hans Verkuil , Nicolas Dufresne , Alex Bee , Arun Iyengar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794615229; l=3973; i=aiyengar1990@gmail.com; s=20261110; h=from:subject:message-id; bh=ChHZwNhLk4WNiGW3BpdABPaZ57+oP++kU/hOOD04E7I=; b=uS4zfwgTX+5ZBvlB6DoFO8TpVG+Ewot7VmL7qXlTShSwggTjUBmz6Sjdtx3T/b/g8AM/3fyXW OodGGE+F1E2BjfrznJDqt+oCdEOPnuvAemYgFKzSd7cWsIejY9oKhrY X-Developer-Key: i=aiyengar1990@gmail.com; a=ed25519; pk=zXpRgUTrhaFe6jLyPqbBy3ccfkj04w0g2690Wv3mg+0= X-Endpoint-Received: by B4 Relay for aiyengar1990@gmail.com/20261110 with auth_id=1480 X-Original-From: Arun Iyengar Content-Transfer-Encoding: 7bit X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: aiyengar1990@gmail.com Sender: "linux-arm-kernel" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, FREEMAIL_REPLYTO_END_DIGIT,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Arun Iyengar Add a binding for the IEP2 deinterlacer of the RK3568 and RK3588 SoCs. It is a different block from the IEP of RK3228/RK3288/RK3328/RK3399, hence "iep2". The RK3588 block falls back to the RK3568 compatible: the vendor kernel drives both with one compatible ("rockchip,iep-v2") and one driver. Clock and reset names follow the RGA binding. The resets are optional: the block has its own soft reset. Signed-off-by: Arun Iyengar --- .../bindings/media/rockchip,rk3568-iep2.yaml | 95 ++++++++++++++++++++++ MAINTAINERS | 7 ++ 2 files changed, 102 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-iep2.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-iep2.yaml new file mode 100644 index 000000000000..0c7666de19f8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-iep2.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,rk3568-iep2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip IEP2 image enhancement processor + +maintainers: + - Arun Iyengar + +description: + Memory to memory video deinterlacer of the Rockchip RK3568 and RK3588 + SoCs. It has its own IOMMU, with which it shares its interrupt line. + +properties: + compatible: + oneOf: + - const: rockchip,rk3568-iep2 + - items: + - const: rockchip,rk3588-iep2 + - const: rockchip,rk3568-iep2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: AXI bus clock + - description: AHB bus clock + - description: Core clock + + clock-names: + items: + - const: aclk + - const: hclk + - const: sclk + + resets: + items: + - description: AXI reset + - description: AHB reset + - description: Core reset + + reset-names: + items: + - const: axi + - const: ahb + - const: core + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - iommus + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + deinterlace@fdbb0000 { + compatible = "rockchip,rk3588-iep2", "rockchip,rk3568-iep2"; + reg = <0x0 0xfdbb0000 0x0 0x500>; + interrupts = ; + clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>, + <&cru CLK_IEP2P0_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_A_IEP2P0>, <&cru SRST_H_IEP2P0>, + <&cru SRST_IEP2P0_CORE>; + reset-names = "axi", "ahb", "core"; + power-domains = <&power RK3588_PD_VDPU>; + iommus = <&iep_mmu>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index f4456f4589a1..b32b7eeb0a9e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24285,6 +24285,13 @@ S: Maintained F: Documentation/devicetree/bindings/sound/rockchip,i2s-tdm.yaml F: sound/soc/rockchip/rockchip_i2s_tdm.* +ROCKCHIP IEP2 DEINTERLACER DRIVER +M: Arun Iyengar +L: linux-media@vger.kernel.org +L: linux-rockchip@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/media/rockchip,rk3568-iep2.yaml + ROCKCHIP ISP V1 DRIVER M: Dafna Hirschfeld M: Laurent Pinchart -- 2.55.0