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Sat, 14 Nov 2026 22:11:24 -0800 (PST) Received: from jernej-laptop ([2a00:ee2:6a02:9300:bb69:6bcf:1b11:e85b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4bb5ba25b50sm139331075e9.14.2026.11.14.22.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2026 22:11:24 -0800 (PST) From: Jernej Skrabec To: Chen-Yu Tsai , Samuel Holland Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, sboyd@kernel.org, Andre Przywara , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 3/8] drm/sun4i: Add support for DE33 CSC Date: Sun, 15 Nov 2026 07:10:57 +0100 Message-ID: <20261115061102.229680-4-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261115061102.229680-1-jernej.skrabec@gmail.com> References: <20261115061102.229680-1-jernej.skrabec@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261114_221128_331792_570EB167 X-CRM114-Status: GOOD ( 16.21 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 DE33 has channel CSC units (for each plane separately) so pipeline can be configured to output in desired colorspace. Reviewed-by: Chen-Yu Tsai Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/sun4i/sun8i_csc.c | 71 +++++++++++++++++++++++++++++++ drivers/gpu/drm/sun4i/sun8i_csc.h | 5 +++ 2 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c index ce81c12f511d..70fc9b017d17 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.c +++ b/drivers/gpu/drm/sun4i/sun8i_csc.c @@ -205,6 +205,72 @@ static void sun8i_de3_ccsc_setup(struct regmap *map, int layer, mask, val); } +/* extract constant from high word and invert sign if necessary */ +static u32 sun8i_de33_ccsc_get_constant(u32 value) +{ + value >>= 16; + + if (value & BIT(15)) + return 0x400 - (value & 0x3ff); + + return value; +} + +static void sun8i_de33_convert_table(const u32 *src, u32 *dst) +{ + dst[0] = sun8i_de33_ccsc_get_constant(src[3]); + dst[1] = sun8i_de33_ccsc_get_constant(src[7]); + dst[2] = sun8i_de33_ccsc_get_constant(src[11]); + memcpy(&dst[3], src, sizeof(u32) * 12); + dst[6] &= 0xffff; + dst[10] &= 0xffff; + dst[14] &= 0xffff; +} + +static void sun8i_de33_ccsc_setup(struct regmap *map, int layer, + enum sun8i_csc_mode mode, + enum drm_color_encoding encoding, + enum drm_color_range range) +{ + u32 addr, val, base, csc[15]; + const u32 *table; + int i; + + table = yuv2rgb_de3[range][encoding]; + base = DE33_CCSC_BASE + layer * DE33_CH_SIZE; + + switch (mode) { + case SUN8I_CSC_MODE_OFF: + val = 0; + break; + case SUN8I_CSC_MODE_YUV2RGB: + val = SUN8I_CSC_CTRL_EN; + sun8i_de33_convert_table(table, csc); + regmap_bulk_write(map, SUN50I_CSC_COEFF(base, 0), csc, 15); + break; + case SUN8I_CSC_MODE_YVU2RGB: + val = SUN8I_CSC_CTRL_EN; + sun8i_de33_convert_table(table, csc); + for (i = 0; i < 15; i++) { + addr = SUN50I_CSC_COEFF(base, i); + if (i > 3) { + if (((i - 3) & 3) == 1) + addr = SUN50I_CSC_COEFF(base, i + 1); + else if (((i - 3) & 3) == 2) + addr = SUN50I_CSC_COEFF(base, i - 1); + } + regmap_write(map, addr, csc[i]); + } + break; + default: + val = 0; + DRM_WARN("Wrong CSC mode specified.\n"); + return; + } + + regmap_write(map, SUN8I_CSC_CTRL(base), val); +} + static u32 sun8i_csc_get_mode(struct drm_plane_state *state) { const struct drm_format_info *format; @@ -238,6 +304,11 @@ void sun8i_csc_config(struct sun8i_layer *layer, mode, state->color_encoding, state->color_range); return; + } else if (layer->cfg->de_type == SUN8I_MIXER_DE33) { + sun8i_de33_ccsc_setup(layer->regs, layer->channel, + mode, state->color_encoding, + state->color_range); + return; } base = ccsc_base[layer->cfg->ccsc][layer->channel]; diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h index 2a4b79599610..d2ba5f8611aa 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.h +++ b/drivers/gpu/drm/sun4i/sun8i_csc.h @@ -18,9 +18,14 @@ struct sun8i_layer; #define CCSC10_OFFSET 0xA0000 #define CCSC11_OFFSET 0xF0000 +#define DE33_CCSC_BASE 0x800 + #define SUN8I_CSC_CTRL(base) ((base) + 0x0) #define SUN8I_CSC_COEFF(base, i) ((base) + 0x10 + 4 * (i)) +#define SUN50I_CSC_COEFF(base, i) ((base) + 0x04 + 4 * (i)) +#define SUN50I_CSC_ALPHA(base) ((base) + 0x40) + #define SUN8I_CSC_CTRL_EN BIT(0) void sun8i_csc_config(struct sun8i_layer *layer, -- 2.43.0