From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6086C4363D for ; Tue, 6 Oct 2020 12:33:08 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D327206F7 for ; Tue, 6 Oct 2020 12:33:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="2u3fs8j7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5D327206F7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arri.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Q57/FvOjhK0oI7blUqxI4HFD80HeL+NI5aQ0anAE2G4=; b=2u3fs8j72AfQ1mtpUwwuygQNM n6Yobw+OK/Pc3HXtaTJZgqJVmNmhmGcgnz9qg2355hP6mxPvIactQ1/IO+4azf5SuR8G1yKMEp7uw LSERKJX3Ax7hzSsntF8DK1aAf7Tpc1eBjxtMt4fk6KGXlK4hqjENffT8F80Pp6Xo9Zm5ujppdiaym y2xws5EmGajQakahhI3ukw5ouTpkFVQ7oO9mCrlJ6podicAJl1sXtpsdhgc8Mm4EUQ3cbjY6rGpd7 2089+XgSmcjXBl9Duz76J+RfTR76oqkvxWOwRQgrkt4elQPgRJSh0hnc3u53l3auWhW9wX/azEb/M SGE7wJ5xA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPm8N-0001mH-Mm; Tue, 06 Oct 2020 12:31:59 +0000 Received: from mailout02.rmx.de ([62.245.148.41]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPm8J-0001ld-UQ for linux-arm-kernel@lists.infradead.org; Tue, 06 Oct 2020 12:31:57 +0000 Received: from kdin01.retarus.com (kdin01.dmz1.retloc [172.19.17.48]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mailout02.rmx.de (Postfix) with ESMTPS id 4C5H060bwnzNl5N; Tue, 6 Oct 2020 14:31:50 +0200 (CEST) Received: from mta.arri.de (unknown [217.111.95.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by kdin01.retarus.com (Postfix) with ESMTPS id 4C5Gzj2lCWz2xbl; Tue, 6 Oct 2020 14:31:29 +0200 (CEST) Received: from n95hx1g2.localnet (192.168.54.66) by mta.arri.de (192.168.100.104) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 6 Oct 2020 14:30:56 +0200 From: Christian Eggers To: David Laight Subject: Re: [PATCH v3 1/3] i2c: imx: Fix reset of I2SR_IAL flag Date: Tue, 6 Oct 2020 14:30:55 +0200 Message-ID: <2080355.2eSLTprjVn@n95hx1g2> Organization: Arnold & Richter Cine Technik GmbH & Co. Betriebs KG In-Reply-To: References: <20201006060528.drh2yoo2dklyntez@pengutronix.de> <20201006105135.28985-2-ceggers@arri.de> MIME-Version: 1.0 X-Originating-IP: [192.168.54.66] X-RMX-ID: 20201006-143135-4C5Gzj2lCWz2xbl-0@kdin01 X-RMX-SOURCE: 217.111.95.66 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_083156_196743_3495F463 X-CRM114-Status: GOOD ( 17.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , Oleksij Rempel , NXP Linux Team , Pengutronix Kernel Team , Uwe =?ISO-8859-1?Q?Kleine=2DK=F6nig?= , Fabio Estevam , "linux-arm-kernel@lists.infradead.org" , "linux-i2c@vger.kernel.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi David, On Tuesday, 6 October 2020, 14:06:36 CEST, David Laight wrote: > From: Christian Eggers > > +static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned > > int bits) +{ > > + unsigned int temp; > > + > > + /* > > + * i2sr_clr_opcode is the value to clear all interrupts. > > + * Here we want to clear only , so we write > > + * ~i2sr_clr_opcode with just toggled. > > + */ > > + temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; > > + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); > > +} > > That looks either wrong or maybe just overcomplicated. Yes, it looks so. > Why isn't: > imx_i2c_write_reg(bits, i2c_imx, IMX_I2C_I2SR); > enough? i.MX requires W1C and Vybrid requires W0C in order to clear status bits. > More usually you just write back the read value of such > 'write 1 to clear' status registers and then act on all > the set bits. This pattern has been suggested by Uwe Klein-Koenig. It works because write access to read-only register bits is ignored, independent whether 0 or 1 is written. W0C is quite unusual, but I didn't design the hardware... The pattern ensures that not accidentally more status bits are cleared than desired. > That ensures you clear all interrupts that were pending. I think that Uwe's intention was not clearing bits which are not handled at this place. Otherwise events may get lost. > If you need to avoid writes of bits that aren't in the > 'clear all interrupts' value then you just need: > bits &= i2c_imx->hwdata->i2sr_clr_opcode; > prior to the write. I think this wouldn't fit the W0C case for Vybrid. Best regards Christian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel