From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm: fix flush_pfn_alias
Date: Mon, 20 Oct 2014 15:39:44 +0200 [thread overview]
Message-ID: <2144086.KBLsLT82pe@wuerfel> (raw)
In-Reply-To: <1413809642-12931-1-git-send-email-js07.lee@gmail.com>
On Monday 20 October 2014 21:54:02 Jungseung Lee wrote:
> L1_CACHE_BYTES could be larger than real L1 cache line size.
> In that case, flush_pfn_alias function would omit to flush last bytes
> as much as L1_CACHE_BYTES - real cache line size.
Can you list an example on what CPU this would happen in the
patch description? Isn't the L1 cache line size always 32 bytes on ARM?
> So fix end address to "to + PAGE_SIZE - 1". The bottom bits of the address
> is LINELEN. that is ignored by mcrr.
>
> Signed-off-by: Jungseung Lee <js07.lee@gmail.com>
Is this needed in stable backports?
Arnd
next prev parent reply other threads:[~2014-10-20 13:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-20 12:54 [PATCH] arm: fix flush_pfn_alias Jungseung Lee
2014-10-20 13:39 ` Arnd Bergmann [this message]
2014-10-20 13:43 ` Will Deacon
2014-10-20 13:47 ` Russell King - ARM Linux
2014-10-20 15:54 ` Jungseung Lee
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