From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2C6FC5475B for ; Wed, 6 Mar 2024 07:20:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pfuRvv+vRE6lUo828MnpU2hyADGpc11wlvVIEA1rkG8=; b=419OavA0uM59Fd blvxQe6m5yeQ8qSU2sgOOLPGRUeLNsYbhYPuqyNHTtsgfwrNTMJ7B6mjnsMINsq8TeAwmAiysc3pR efWPLqiDnBoCl6PwL/J0jnHelUDvaG6lFNRTB+4I8KmrXSYBSrkZaT9hQLc0i7bHjOZCfH20TP9HR NYKaGRJo5uW4fuuBx4QUw6w215nERqOWwMt1i6ofj2xfpQvc5v7bjfzFSLJuWmgVMMyThm916RO5S tlJg/xz7if/X8qZbC5n24UI1B7PZ8SbvhkO6BfZ1oe3O+OiktbpYkoRwFXJxnT6RfOevd8Sh6xE9/ CAI++ThoNmU3ZqRUcrcQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rhlZU-0000000GgA8-2fZD; Wed, 06 Mar 2024 07:20:12 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rhlZR-0000000Gg77-49f3 for linux-arm-kernel@lists.infradead.org; Wed, 06 Mar 2024 07:20:12 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1709709610; x=1741245610; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jW3nFBn6TcQTAHKIo2UTCLyc402JWm2+7QktnDYTndE=; b=iEzuAD0ugSXiVUxMut+WTkg2rPGKAZUqwk/Q0YTMvC6clVqhp3Oq2P0S IJ7UwxI0KLO0iIwslURZNoDkHzyFGDEnxoGKH3wT0fpIuSmQRv+tB09Ta ah0LX6mRFC2YGzi1ZVeBy/Yiwl8KBewZNSJNwgyCiWDQg93Br0GzJRyTg WnI/89qC9E/ZN5xDU/8QxU+MJxmSDxutwlsJuePAjyqAqFvGU6giy63VH Xee2nevsrzLOR+TzuGK1svfXfmvbI4HkziJNWVccatZ2pgFmaqIoaO3AA M6EU1gwKtPcYclfyDUFRULwdiafNP3ukDmOpKWEQA5Y9ILmC9l07ynOIi Q==; X-IronPort-AV: E=Sophos;i="6.06,207,1705359600"; d="scan'208";a="35754710" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 06 Mar 2024 08:19:58 +0100 Received: from steina-w.localnet (steina-w.tq-net.de [10.123.53.25]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 9EF8D280071; Wed, 6 Mar 2024 08:19:58 +0100 (CET) From: Alexander Stein To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Shengjiu Wang , linux-arm-kernel@lists.infradead.org, Frank Li Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Li Subject: Re: [PATCH v4 4/4] arm64: dts: imx8qxp: add asrc[0, 1], esai0, spdif[0, 1] and sai[4, 5] Date: Wed, 06 Mar 2024 08:20:00 +0100 Message-ID: <2177674.irdbgypaU6@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20240305-asrc_8qxp-v4-4-c61b98046591@nxp.com> References: <20240305-asrc_8qxp-v4-0-c61b98046591@nxp.com> <20240305-asrc_8qxp-v4-4-c61b98046591@nxp.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240305_232010_444086_A52C2BFF X-CRM114-Status: GOOD ( 16.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Frank, thanks for the patch. Am Dienstag, 5. M=E4rz 2024, 18:33:05 CET schrieb Frank Li: > Add asrc[0,1], esai0, spdif[0,1], sai[4,5] and related lpcg node for > imx8 audio subsystem. > = > Signed-off-by: Frank Li > --- > arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 304 +++++++++++++++++= ++++++ > 1 file changed, 304 insertions(+) > = > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8-ss-audio.dtsi > index 07afeb78ed564..78305559f15c9 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > @@ -6,6 +6,7 @@ > = > #include > #include > +#include > #include > = > audio_ipg_clk: clock-audio-ipg { > @@ -481,4 +482,307 @@ acm: acm@59e00000 { > "sai3_rx_bclk", > "sai4_rx_bclk"; > }; > + > + asrc0: asrc@59000000 { Please insert nodes sorted by address. ASRC0 is the very first node. > + compatible =3D "fsl,imx8qm-asrc"; > + reg =3D <0x59000000 0x10000>; > + interrupts =3D ; > + clocks =3D <&asrc0_lpcg 0>, > + <&asrc0_lpcg 0>, > + <&aud_pll_div0_lpcg 0>, > + <&aud_pll_div1_lpcg 0>, > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names =3D "mem", "ipg", > + "asrck_0", "asrck_1", "asrck_2", "asrck_3", > + "asrck_4", "asrck_5", "asrck_6", "asrck_7", > + "asrck_8", "asrck_9", "asrck_a", "asrck_b", > + "asrck_c", "asrck_d", "asrck_e", "asrck_f", > + "spba"; > + dmas =3D <&edma0 0 0 0>, > + <&edma0 1 0 0>, > + <&edma0 2 0 0>, > + <&edma0 3 0 FSL_EDMA_RX>, > + <&edma0 4 0 FSL_EDMA_RX>, > + <&edma0 5 0 FSL_EDMA_RX>; > + /* tx* is output channel of asrc, it is rx channel for eDMA */ > + dma-names =3D "rxa", "rxb", "rxc", "txa", "txb", "txc"; > + fsl,asrc-rate =3D <8000>; > + fsl,asrc-width =3D <16>; > + fsl,asrc-clk-map =3D <0>; > + power-domains =3D <&pd IMX_SC_R_ASRC_0>; > + status =3D "disabled"; > + }; > + > + esai0: esai@59010000 { > + compatible =3D "fsl,imx8qm-esai", "fsl,imx6ull-esai"; > + reg =3D <0x59010000 0x10000>; > + interrupts =3D ; > + clocks =3D <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_du= mmy>; > + clock-names =3D "core", "extal", "fsys", "spba"; > + dmas =3D <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>; > + dma-names =3D "rx", "tx"; > + power-domains =3D <&pd IMX_SC_R_ESAI_0>; > + status =3D "disabled"; > + }; > + > + spdif0: spdif@59020000 { > + compatible =3D "fsl,imx8qm-spdif"; > + reg =3D <0x59020000 0x10000>; > + interrupts =3D , /* rx */ > + ; /* tx */ > + clocks =3D <&spdif0_lpcg 1>, /* core */ > + <&clk_dummy>, /* rxtx0 */ > + <&spdif0_lpcg 0>, /* rxtx1 */ > + <&clk_dummy>, /* rxtx2 */ > + <&clk_dummy>, /* rxtx3 */ > + <&clk_dummy>, /* rxtx4 */ > + <&audio_ipg_clk>, /* rxtx5 */ > + <&clk_dummy>, /* rxtx6 */ > + <&clk_dummy>, /* rxtx7 */ > + <&clk_dummy>; /* spba */ > + clock-names =3D "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", > + "rxtx5", "rxtx6", "rxtx7", "spba"; > + dmas =3D <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, > + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>; > + dma-names =3D "rx", "tx"; > + power-domains =3D <&pd IMX_SC_R_SPDIF_0>; > + status =3D "disabled"; > + }; > + > + spdif1: spdif@59030000 { That's imx8qm only, no? > + compatible =3D "fsl,imx8qm-spdif"; > + reg =3D <0x59030000 0x10000>; > + interrupts =3D , /* rx */ > + ; /* tx */ > + clocks =3D <&spdif1_lpcg 1>, /* core */ > + <&clk_dummy>, /* rxtx0 */ > + <&spdif1_lpcg 0>, /* rxtx1 */ > + <&clk_dummy>, /* rxtx2 */ > + <&clk_dummy>, /* rxtx3 */ > + <&clk_dummy>, /* rxtx4 */ > + <&audio_ipg_clk>, /* rxtx5 */ > + <&clk_dummy>, /* rxtx6 */ > + <&clk_dummy>, /* rxtx7 */ > + <&clk_dummy>; /* spba */ > + clock-names =3D "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", > + "rxtx5", "rxtx6", "rxtx7", "spba"; > + dmas =3D <&edma0 10 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, > + <&edma0 11 0 FSL_EDMA_MULTI_FIFO>; > + dma-names =3D "rx", "tx"; > + power-domains =3D <&pd IMX_SC_R_SPDIF_1>; > + status =3D "disabled"; > + }; > + > + asrc1: asrc@59800000 { Insert this between dsp and edma1, sorted by address. > + compatible =3D "fsl,imx8qm-asrc"; > + reg =3D <0x59800000 0x10000>; > + interrupts =3D ; > + clocks =3D <&asrc1_lpcg 0>, > + <&asrc1_lpcg 0>, > + <&aud_pll_div0_lpcg 0>, > + <&aud_pll_div1_lpcg 0>, > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names =3D "mem", "ipg", > + "asrck_0", "asrck_1", "asrck_2", "asrck_3", > + "asrck_4", "asrck_5", "asrck_6", "asrck_7", > + "asrck_8", "asrck_9", "asrck_a", "asrck_b", > + "asrck_c", "asrck_d", "asrck_e", "asrck_f", > + "spba"; > + dmas =3D <&edma1 0 0 0>, > + <&edma1 1 0 0>, > + <&edma1 2 0 0>, > + <&edma1 3 0 FSL_EDMA_RX>, > + <&edma1 4 0 FSL_EDMA_RX>, > + <&edma1 5 0 FSL_EDMA_RX>; > + /* tx* is output channel of asrc, it is rx channel for eDMA */ > + dma-names =3D "rxa", "rxb", "rxc", "txa", "txb", "txc"; > + fsl,asrc-rate =3D <8000>; > + fsl,asrc-width =3D <16>; > + fsl,asrc-clk-map =3D <1>; > + power-domains =3D <&pd IMX_SC_R_ASRC_1>; > + status =3D "disabled"; > + }; > + > + sai4: sai@59820000 { > + compatible =3D "fsl,imx8qm-sai"; > + reg =3D <0x59820000 0x10000>; > + interrupts =3D ; > + clocks =3D <&sai4_lpcg 1>, > + <&clk_dummy>, > + <&sai4_lpcg 0>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names =3D "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas =3D <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>; > + dma-names =3D "rx", "tx"; > + power-domains =3D <&pd IMX_SC_R_SAI_4>; > + status =3D "disabled"; > + }; > + > + sai5: sai@59830000 { > + compatible =3D "fsl,imx8qm-sai"; > + reg =3D <0x59830000 0x10000>; > + interrupts =3D ; > + clocks =3D <&sai5_lpcg 1>, > + <&clk_dummy>, > + <&sai5_lpcg 0>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names =3D "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas =3D <&edma1 10 0 0>; > + dma-names =3D "tx"; > + power-domains =3D <&pd IMX_SC_R_SAI_5>; > + status =3D "disabled"; > + }; > + > + amix: amix@59840000 { > + compatible =3D "fsl,imx8qm-audmix"; > + reg =3D <0x59840000 0x10000>; > + clocks =3D <&amix_lpcg 0>; > + clock-names =3D "ipg"; > + power-domains =3D <&pd IMX_SC_R_AMIX>; > + dais =3D <&sai4>, <&sai5>; > + status =3D "disabled"; > + }; > + > + mqs: mqs@59850000 { > + compatible =3D "fsl,imx8qm-mqs"; > + reg =3D <0x59850000 0x10000>; > + clocks =3D <&mqs0_lpcg 0>, > + <&mqs0_lpcg 1>; > + clock-names =3D "mclk", "core"; > + power-domains =3D <&pd IMX_SC_R_MQS_0>; > + status =3D "disabled"; > + }; > + > + asrc0_lpcg: clock-controller@59400000 { Please insert he lpcg nodes according to their address. > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x59400000 0x10000>; > + #clock-cells =3D <1>; > + clocks =3D <&audio_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "asrc0_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_ASRC_0>; > + }; > + > + esai0_lpcg: clock-controller@59410000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x59410000 0x10000>; > + #clock-cells =3D <1>; > + clocks =3D <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "esai0_lpcg_extal_clk", > + "esai0_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_ESAI_0>; > + }; > + > + spdif0_lpcg: clock-controller@59420000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x59420000 0x10000>; > + #clock-cells =3D <1>; > + clocks =3D <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "spdif0_lpcg_tx_clk", > + "spdif0_lpcg_gclkw"; > + power-domains =3D <&pd IMX_SC_R_SPDIF_0>; > + }; > + > + spdif1_lpcg: clock-controller@59430000 { That's imx8qm only as well, no? Thanks and best regards, Alexander > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x59430000 0x10000>; > + #clock-cells =3D <1>; > + clocks =3D <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "spdif1_lpcg_tx_clk", > + "spdif1_lpcg_gclkw"; > + power-domains =3D <&pd IMX_SC_R_SPDIF_1>; > + status =3D "disabled"; > + }; > + > + asrc1_lpcg: clock-controller@59c00000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x59c00000 0x10000>; > + #clock-cells =3D <1>; > + clocks =3D <&audio_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "asrc1_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_ASRC_1>; > + }; > + > + sai4_lpcg: clock-controller@59c20000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x59c20000 0x10000>; > + #clock-cells =3D <1>; > + clocks =3D <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "sai4_lpcg_mclk", > + "sai4_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_SAI_4>; > + }; > + > + sai5_lpcg: clock-controller@59c30000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x59c30000 0x10000>; > + #clock-cells =3D <1>; > + clocks =3D <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "sai5_lpcg_mclk", > + "sai5_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_SAI_5>; > + }; > + > + amix_lpcg: clock-controller@59c40000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x59c40000 0x10000>; > + #clock-cells =3D <1>; > + clocks =3D <&audio_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "amix_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_AMIX>; > + }; > + > + mqs0_lpcg: clock-controller@59c50000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x59c50000 0x10000>; > + #clock-cells =3D <1>; > + clocks =3D <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "mqs0_lpcg_mclk", > + "mqs0_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MQS_0>; > + }; > }; > = > = -- = TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel