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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jVnDp-0003Mg-O4; Tue, 05 May 2020 02:22:13 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jVnDm-0003Kn-Fk for linux-arm-kernel@lists.infradead.org; Tue, 05 May 2020 02:22:12 +0000 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 2746F1C450F457EED3C6; Tue, 5 May 2020 10:21:55 +0800 (CST) Received: from [127.0.0.1] (10.74.221.148) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.487.0; Tue, 5 May 2020 10:21:52 +0800 Subject: Re: [PATCH] arm64: perf: Expose some new events via sysfs To: Will Deacon References: <1587450713-18048-1-git-send-email-zhangshaokun@hisilicon.com> <20200501171237.GA19048@willie-the-truck> <970b8ae4-fd9a-d5d1-0066-92152ff07fd5@hisilicon.com> <20200504070624.GB2183@willie-the-truck> From: Shaokun Zhang Message-ID: <21e52d92-1cff-bf62-3d98-cd1150e56373@hisilicon.com> Date: Tue, 5 May 2020 10:21:52 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <20200504070624.GB2183@willie-the-truck> X-Originating-IP: [10.74.221.148] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200504_192210_692063_38A9659E X-CRM114-Status: GOOD ( 11.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On 2020/5/4 15:06, Will Deacon wrote: > On Mon, May 04, 2020 at 11:46:14AM +0800, Shaokun Zhang wrote: >> Hi Will, >> >> One more question;-) >> >> On 2020/5/2 1:12, Will Deacon wrote: >>> On Tue, Apr 21, 2020 at 02:31:53PM +0800, Shaokun Zhang wrote: >>>> Some new PMU events can been detected by PMCEID1_EL0, but it can't >>>> be listed, Let's expose these through sysfs. >>>> >>>> Cc: Will Deacon >>>> Cc: Mark Rutland >>>> Signed-off-by: Shaokun Zhang >>>> --- >>>> arch/arm64/include/asm/perf_event.h | 19 +++++++++++++++++++ >>>> arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++ >>>> 2 files changed, 38 insertions(+) >>>> >>>> diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h >>>> index e7765b62c712..f1b93d7c4260 100644 >>>> --- a/arch/arm64/include/asm/perf_event.h >>>> +++ b/arch/arm64/include/asm/perf_event.h >>>> @@ -72,12 +72,31 @@ >>>> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36 >>>> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37 >>>> #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38 >>>> +#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39 >>>> +#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A >>>> +#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B >>>> +#define ARMV8_PMUV3_PERFCTR_STALL 0x3C >>>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D >>>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E >>>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F >>> >>> Hmm, looks like the presence of this event implies the presence of the >>> PMMIR_EL1 register. Should we be exposing the "SLOTS" field from that in >>> sysfs? (obviously as a separate patch) >>> >> >> Shall I expose it in /sys/devices/system/cpu/cpuX/regs/, right? > > No; if we need to expose it (do we?) then it should be alongside the other It seems that we need it if the PMU version is equal or greater than ARMv8.4-PMU. > PMU files. e.g. /sys/bus/event_source/$pmu_name/caps/slots > Got it, I did it as /sys/bus/event_source/devices/armv8_pmuv3_0/caps/slots or /sys/devices/armv8_pmuv3_0/caps/slots. Thanks, Shaokun > Will > > . > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel