From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DBC8C3DA4A for ; Mon, 29 Jul 2024 04:41:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QjUST734sD7rWQ37ckXjjW+LzXyAASy26ZU/AHO72OI=; b=3YKBIzugDI34xMW0+7hyVL9Wbv YM5WbCqfwt5PL2CkaXNCSq42CiNvr6nv9SUcRqW5Spf1YWAefMkRp3fN/byL7fGpptVfPAIThDL2h N0Xt/sINAerzCWlUfuKLtIdlaB1NeWk/meStUQ52x+lW415UKzaO1Rp9jFS/NRDAK2vT2eSI1SdoR dss5H+E5zh5+3TsEd4P4PvFYilHSFsi1kKchasmYQzQx+shbDad5Um92GT3mHv2/HRismnvaOiJru qksOW5sgzslBJw7j5TdFi4ytE4RLqJaKcJUrP1fgjr2VpCy/T6NV9qgw0ysnb4ftDgAyK0kPHC7Oa VcjY4EoA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYIC2-00000009yoc-2cRy; Mon, 29 Jul 2024 04:41:06 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYIBc-00000009ymk-3xxE for linux-arm-kernel@lists.infradead.org; Mon, 29 Jul 2024 04:40:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3AF72FEC; Sun, 28 Jul 2024 21:41:02 -0700 (PDT) Received: from [10.162.41.10] (a077893.blr.arm.com [10.162.41.10]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C2C083F5A1; Sun, 28 Jul 2024 21:40:35 -0700 (PDT) Message-ID: <22011be2-484d-47ec-9f5b-6b3104e47c9f@arm.com> Date: Mon, 29 Jul 2024 10:10:32 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 0/3] aarch64: Enable access for FEAT_D128 registers in EL1/EL2 To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com References: <20240729043606.871451-1-anshuman.khandual@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20240729043606.871451-1-anshuman.khandual@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240728_214041_066685_DFB072BF X-CRM114-Status: GOOD ( 11.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/29/24 10:06, Anshuman Khandual wrote: > This series enables access for FEAT_D128 relevant registers in EL1/EL2 via > setting respective bits in SCR_EL3, when their corresponding features are > detected. > > -------------------------------------------------------------- > | FEAT_D128 | ID_AA64MMFR3_EL1_D128 | SCR_EL3_D128En | > | FEAT_SCTLR2 | ID_AA64MMFR3_EL1_SCTLRX | SCR_EL3_SCTLR2En | > | FEAT_THE | ID_AA64PFR1_EL1_THE | SCR_EL3_RCWMASKEn | > -------------------------------------------------------------- > > Changes in V2: > > - Moved up the patch related to SCTLR2_ELx from [PATCH 2/3] to [PATCH 1/3] > - Updated the commit message for the above mentioned patch > - Fixed the commit message s/D128En/SCTLR2En as the enabling bit > - Reset SCTLR2_ELx registers so that unaware kernels do not get surprises > > Changes in V1: > > https://lore.kernel.org/all/20240723110630.483871-1-anshuman.khandual@arm.com/ > > Anshuman Khandual (3): > aarch64: Enable access into SCTLR2_ELx registers from EL2 and below > aarch64: Enable access into 128 bit system registers from EL2 and below > aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below > > arch/aarch64/include/asm/cpu.h | 11 ++++++++++- > arch/aarch64/init.c | 12 ++++++++++++ > 2 files changed, 22 insertions(+), 1 deletion(-) > Oops, forgot to change PATCH as boot-wrapper for differentiation once again.