* [PATCH v2 01/10] nvmem: imx-ocotp: Sort header alphabetically
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 8:36 ` [PATCH v2 02/10] nvmem: imx-ocotp: Support accessing controller for i.MX8M Alexander Stein
` (8 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel,
Frank Li
Move linux/delay.h to the right position.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
drivers/nvmem/imx-ocotp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 79dd4fda03295..c5086a16450ac 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -15,6 +15,7 @@
*/
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -22,7 +23,6 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
-#include <linux/delay.h>
#define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
* OTP Bank0 Word0
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 02/10] nvmem: imx-ocotp: Support accessing controller for i.MX8M
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
2025-02-07 8:36 ` [PATCH v2 01/10] nvmem: imx-ocotp: Sort header alphabetically Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 15:22 ` Frank Li
2025-02-07 8:36 ` [PATCH v2 03/10] arm64: dts: imx8mn: Add i.MX8M Nano OCOTP disable fuse definitions Alexander Stein
` (7 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel
i.MX8M OCOTP supports a specific peripheral or function being fused
which means disabled, so
- Introduce disable_fuse for a list of possible fused peripherals.
- Iterate all nodes to check accessing permission. If not
allowed to be accessed, detach the node
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
drivers/nvmem/Kconfig | 3 ++
drivers/nvmem/imx-ocotp.c | 74 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 8671b7c974b93..ba5c928cab520 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -84,6 +84,9 @@ config NVMEM_IMX_OCOTP
This driver can also be built as a module. If so, the module
will be called nvmem-imx-ocotp.
+ If built as modules, any other driver relying on this working
+ as access controller also needs to be a module as well.
+
config NVMEM_IMX_OCOTP_ELE
tristate "i.MX On-Chip OTP Controller support"
depends on ARCH_MXC || COMPILE_TEST
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index c5086a16450ac..b15cbdae66a7c 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -589,6 +589,74 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
cell->read_post_process = imx_ocotp_cell_pp;
}
+static int imx_ocotp_check_access(struct ocotp_priv *priv, u32 addr, u32 bit)
+{
+ u32 mask, ret, val;
+
+ mask = BIT(bit);
+
+ ret = imx_ocotp_read(priv, addr, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ /* true means disabled */
+ if (val & mask)
+ return -EACCES;
+
+ return 0;
+}
+
+static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent)
+{
+ struct device *dev = priv->dev;
+
+ for_each_available_child_of_node_scoped(parent, child) {
+ struct of_phandle_args args;
+ u32 idx = 0;
+ u32 addr;
+ u32 bit;
+
+ while (!of_parse_phandle_with_args(child, "access-controllers",
+ "#access-controller-cells",
+ idx++, &args)) {
+ of_node_put(args.np);
+ if (args.np != dev->of_node)
+ continue;
+
+ /* Only support one cell */
+ if (args.args_count != 2) {
+ dev_err(dev, "wrong args count\n");
+ continue;
+ }
+
+ addr = args.args[0];
+ bit = args.args[1];
+
+ dev_dbg(dev, "Checking node: %pOF disable fuse addr: %u, bit %u\n", child, addr, bit);
+
+ if (imx_ocotp_check_access(priv, addr, bit)) {
+ of_detach_node(child);
+ dev_info(dev, "%pOF: disabled by fuse, device driver will not be probed\n",
+ child);
+ }
+ }
+
+ imx_ocotp_grant_access(priv, child);
+ }
+
+ return 0;
+}
+
+static int imx_ocotp_access_control(struct ocotp_priv *priv)
+{
+ struct device_node *root __free(device_node) = of_find_node_by_path("/");
+
+ if (WARN_ON(!root))
+ return -EINVAL;
+
+ return imx_ocotp_grant_access(priv, root);
+}
+
static int imx_ocotp_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -622,9 +690,13 @@ static int imx_ocotp_probe(struct platform_device *pdev)
imx_ocotp_clr_err_if_set(priv);
clk_disable_unprepare(priv->clk);
+ platform_set_drvdata(pdev, priv);
+
nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
+ if (IS_ERR(nvmem))
+ return PTR_ERR(nvmem);
- return PTR_ERR_OR_ZERO(nvmem);
+ return imx_ocotp_access_control(priv);
}
static struct platform_driver imx_ocotp_driver = {
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 02/10] nvmem: imx-ocotp: Support accessing controller for i.MX8M
2025-02-07 8:36 ` [PATCH v2 02/10] nvmem: imx-ocotp: Support accessing controller for i.MX8M Alexander Stein
@ 2025-02-07 15:22 ` Frank Li
0 siblings, 0 replies; 23+ messages in thread
From: Frank Li @ 2025-02-07 15:22 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree, imx, linux-arm-kernel,
linux-kernel
On Fri, Feb 07, 2025 at 09:36:07AM +0100, Alexander Stein wrote:
> i.MX8M OCOTP supports a specific peripheral or function being fused
> which means disabled, so
> - Introduce disable_fuse for a list of possible fused peripherals.
> - Iterate all nodes to check accessing permission. If not
> allowed to be accessed, detach the node
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> drivers/nvmem/Kconfig | 3 ++
> drivers/nvmem/imx-ocotp.c | 74 ++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 76 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> index 8671b7c974b93..ba5c928cab520 100644
> --- a/drivers/nvmem/Kconfig
> +++ b/drivers/nvmem/Kconfig
> @@ -84,6 +84,9 @@ config NVMEM_IMX_OCOTP
> This driver can also be built as a module. If so, the module
> will be called nvmem-imx-ocotp.
>
> + If built as modules, any other driver relying on this working
> + as access controller also needs to be a module as well.
> +
> config NVMEM_IMX_OCOTP_ELE
> tristate "i.MX On-Chip OTP Controller support"
> depends on ARCH_MXC || COMPILE_TEST
> diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
> index c5086a16450ac..b15cbdae66a7c 100644
> --- a/drivers/nvmem/imx-ocotp.c
> +++ b/drivers/nvmem/imx-ocotp.c
> @@ -589,6 +589,74 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
> cell->read_post_process = imx_ocotp_cell_pp;
> }
>
> +static int imx_ocotp_check_access(struct ocotp_priv *priv, u32 addr, u32 bit)
> +{
> + u32 mask, ret, val;
> +
> + mask = BIT(bit);
> +
> + ret = imx_ocotp_read(priv, addr, &val, sizeof(val));
> + if (ret)
> + return ret;
> +
> + /* true means disabled */
> + if (val & mask)
> + return -EACCES;
> +
> + return 0;
> +}
> +
> +static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent)
> +{
> + struct device *dev = priv->dev;
> +
> + for_each_available_child_of_node_scoped(parent, child) {
> + struct of_phandle_args args;
> + u32 idx = 0;
> + u32 addr;
> + u32 bit;
> +
> + while (!of_parse_phandle_with_args(child, "access-controllers",
> + "#access-controller-cells",
> + idx++, &args)) {
> + of_node_put(args.np);
> + if (args.np != dev->of_node)
> + continue;
> +
> + /* Only support one cell */
nit: two cell?
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> + if (args.args_count != 2) {
> + dev_err(dev, "wrong args count\n");
> + continue;
> + }
> +
> + addr = args.args[0];
> + bit = args.args[1];
> +
> + dev_dbg(dev, "Checking node: %pOF disable fuse addr: %u, bit %u\n", child, addr, bit);
> +
> + if (imx_ocotp_check_access(priv, addr, bit)) {
> + of_detach_node(child);
> + dev_info(dev, "%pOF: disabled by fuse, device driver will not be probed\n",
> + child);
> + }
> + }
> +
> + imx_ocotp_grant_access(priv, child);
> + }
> +
> + return 0;
> +}
> +
> +static int imx_ocotp_access_control(struct ocotp_priv *priv)
> +{
> + struct device_node *root __free(device_node) = of_find_node_by_path("/");
> +
> + if (WARN_ON(!root))
> + return -EINVAL;
> +
> + return imx_ocotp_grant_access(priv, root);
> +}
> +
> static int imx_ocotp_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -622,9 +690,13 @@ static int imx_ocotp_probe(struct platform_device *pdev)
> imx_ocotp_clr_err_if_set(priv);
> clk_disable_unprepare(priv->clk);
>
> + platform_set_drvdata(pdev, priv);
> +
> nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
> + if (IS_ERR(nvmem))
> + return PTR_ERR(nvmem);
>
> - return PTR_ERR_OR_ZERO(nvmem);
> + return imx_ocotp_access_control(priv);
> }
>
> static struct platform_driver imx_ocotp_driver = {
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 03/10] arm64: dts: imx8mn: Add i.MX8M Nano OCOTP disable fuse definitions
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
2025-02-07 8:36 ` [PATCH v2 01/10] nvmem: imx-ocotp: Sort header alphabetically Alexander Stein
2025-02-07 8:36 ` [PATCH v2 02/10] nvmem: imx-ocotp: Support accessing controller for i.MX8M Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 11:54 ` Peng Fan
2025-02-07 8:36 ` [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references Alexander Stein
` (6 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel
These definitions define the location of corresponding disable bits
in OCOTP peripheral.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8mn-ocotp.h | 26 ++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ocotp.h
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mn-ocotp.h
new file mode 100644
index 0000000000000..43583c4a70156
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ocotp.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+#ifndef __DTS_IMX8MN_OCOTP_H
+#define __DTS_IMX8MN_OCOTP_H
+
+/*
+ * The OCOTP is a tuple of
+ * <fuse_addr fuse_bit_offset>
+ */
+
+#define IMX8MN_OCOTP_M7_DISABLE 20 8
+#define IMX8MN_OCOTP_M7_MPU_DISABLE 20 9
+#define IMX8MN_OCOTP_M7_FPU_DISABLE 20 10
+#define IMX8MN_OCOTP_USB_OTG1_DISABLE 20 11
+#define IMX8MN_OCOTP_GPU3D_DISABLE 20 24
+#define IMX8MN_OCOTP_MIPI_DSI_DISABLE 20 28
+#define IMX8MN_OCOTP_ENET_DISABLE 20 29
+#define IMX8MN_OCOTP_MIPI_CSI_DISABLE 20 30
+#define IMX8MN_OCOTP_ASRC_DISABLE 20 31
+
+#endif /* __DTS_IMX8MN_OCOTP_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 03/10] arm64: dts: imx8mn: Add i.MX8M Nano OCOTP disable fuse definitions
2025-02-07 8:36 ` [PATCH v2 03/10] arm64: dts: imx8mn: Add i.MX8M Nano OCOTP disable fuse definitions Alexander Stein
@ 2025-02-07 11:54 ` Peng Fan
0 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2025-02-07 11:54 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree, imx, linux-arm-kernel,
linux-kernel
On Fri, Feb 07, 2025 at 09:36:08AM +0100, Alexander Stein wrote:
>These definitions define the location of corresponding disable bits
>in OCOTP peripheral.
>
>Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
` (2 preceding siblings ...)
2025-02-07 8:36 ` [PATCH v2 03/10] arm64: dts: imx8mn: Add i.MX8M Nano OCOTP disable fuse definitions Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 12:02 ` Peng Fan
2025-02-07 8:36 ` [PATCH v2 05/10] arm64: dts: imx8mp: Add i.MX8M Plus OCOTP disable fuse definitions Alexander Stein
` (5 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel
Mark ocotp as a access-controller and add references on peripherals
which can be disabled (fused).
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index a5f9cfb46e5dd..ee6c3a4be87fd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
+#include "imx8mn-ocotp.h"
#include "imx8mn-pinfunc.h"
/ {
@@ -431,6 +432,7 @@ easrc: easrc@300c0000 {
firmware-name = "imx/easrc/easrc-imx8mn.bin";
fsl,asrc-rate = <8000>;
fsl,asrc-format = <2>;
+ access-controllers = <&ocotp IMX8MN_OCOTP_ASRC_DISABLE>;
status = "disabled";
};
};
@@ -571,6 +573,7 @@ ocotp: efuse@30350000 {
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
#address-cells = <1>;
#size-cells = <1>;
+ #access-controller-cells = <2>;
/*
* The register address below maps to the MX8M
@@ -1053,6 +1056,7 @@ fec1: ethernet@30be0000 {
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
fsl,stop-mode = <&gpr 0x10 3>;
+ access-controllers = <&ocotp IMX8MN_OCOTP_ENET_DISABLE>;
status = "disabled";
};
@@ -1091,6 +1095,7 @@ mipi_dsi: dsi@32e10000 {
clock-names = "bus_clk", "sclk_mipi";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
+ access-controllers = <&ocotp IMX8MN_OCOTP_MIPI_DSI_DISABLE>;
status = "disabled";
ports {
@@ -1195,6 +1200,7 @@ mipi_csi: mipi-csi@32e30000 {
<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
+ access-controllers = <&ocotp IMX8MN_OCOTP_MIPI_CSI_DISABLE>;
status = "disabled";
ports {
@@ -1225,6 +1231,7 @@ usbotg1: usb@32e40000 {
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_hsiomix>;
+ access-controllers = <&ocotp IMX8MN_OCOTP_USB_OTG1_DISABLE>;
status = "disabled";
};
@@ -1288,6 +1295,7 @@ gpu: gpu@38000000 {
<400000000>,
<1200000000>;
power-domains = <&pgc_gpumix>;
+ access-controllers = <&ocotp IMX8MN_OCOTP_GPU3D_DISABLE>;
};
gic: interrupt-controller@38800000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references
2025-02-07 8:36 ` [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references Alexander Stein
@ 2025-02-07 12:02 ` Peng Fan
2025-02-07 12:37 ` Alexander Stein
0 siblings, 1 reply; 23+ messages in thread
From: Peng Fan @ 2025-02-07 12:02 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree, imx, linux-arm-kernel,
linux-kernel
On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote:
>Mark ocotp as a access-controller and add references on peripherals
>which can be disabled (fused).
I am not sure whether gpcv2 changes should be included in this patchset
or not. Just add access-controller for fused IP will not work.
i.MX8M BLK-CTRL/GPC will hang if the related power domain is still touched
by kernel. The pgc can't power up/down because clock is gated.
This comment also apply to i.MX8MM/P.
Regards
Peng
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references
2025-02-07 12:02 ` Peng Fan
@ 2025-02-07 12:37 ` Alexander Stein
2025-02-10 2:36 ` Peng Fan
0 siblings, 1 reply; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 12:37 UTC (permalink / raw)
To: Peng Fan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree, imx, linux-arm-kernel,
linux-kernel
Hi Peng,
Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan:
> On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote:
> >Mark ocotp as a access-controller and add references on peripherals
> >which can be disabled (fused).
>
> I am not sure whether gpcv2 changes should be included in this patchset
> or not. Just add access-controller for fused IP will not work.
Well, I was able to successfully boot a i.MX8M Nano DualLite.
> i.MX8M BLK-CTRL/GPC will hang if the related power domain is still touched
> by kernel. The pgc can't power up/down because clock is gated.
Well, with GPU node disabled, no one should enable the power domain.
But to be on the safe side I would also add access-controllers to the
corresponding power domains as well.
> This comment also apply to i.MX8MM/P.
Sure. Do you have any information what is actually disabled by those fused?
It seems it's the IP and their power domains. Anything else?
Best regards,
Alexander
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references
2025-02-07 12:37 ` Alexander Stein
@ 2025-02-10 2:36 ` Peng Fan
2025-02-10 15:48 ` Alexander Stein
0 siblings, 1 reply; 23+ messages in thread
From: Peng Fan @ 2025-02-10 2:36 UTC (permalink / raw)
To: Alexander Stein, Peng Fan (OSS)
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-
> controller references
>
> Hi Peng,
>
> Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan:
> > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote:
> > >Mark ocotp as a access-controller and add references on peripherals
> > >which can be disabled (fused).
> >
> > I am not sure whether gpcv2 changes should be included in this
> > patchset or not. Just add access-controller for fused IP will not work.
>
> Well, I was able to successfully boot a i.MX8M Nano DualLite.
>
> > i.MX8M BLK-CTRL/GPC will hang if the related power domain is still
> > touched by kernel. The pgc can't power up/down because clock is
> gated.
>
> Well, with GPU node disabled, no one should enable the power domain.
> But to be on the safe side I would also add access-controllers to the
> corresponding power domains as well.
>
> > This comment also apply to i.MX8MM/P.
>
> Sure. Do you have any information what is actually disabled by those
> fused?
> It seems it's the IP and their power domains. Anything else?
In NXP downstream there is a patch for drivers/pmdomain/imx/imx8m-blk-ctrl.c
soc: imx8m-blk-ctrl: Support fused modules
For fused module, its pgc can't power up/down and clock is gated.
Because imx8m-blk-ctrl driver will pm_runtime_get_sync/pm_runtime_put
all power domains during suspend/resume. So we have to remove the
pgc and clock of fused module from blk-ctrl DTS node.
Update the driver to support such case.
But this patch also needs U-Boot to update device tree nodes,
I recalled that U-Boot will remove gpc nodes, but not update blk-ctrl nodes.
Regards,
Peng.
>
> Best regards,
> Alexander
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld,
> Germany Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> www.tq-
> group.com%2F&data=05%7C02%7Cpeng.fan%40nxp.com%7Ca7392a7
> a9a7d480f69c108dd477447bc%7C686ea1d3bc2b4c6fa92cd99c5c301
> 635%7C0%7C0%7C638745286928288330%7CUnknown%7CTWFpbGZ
> sb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW
> 4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=F
> R%2BeuYsheLUO8UY6sB%2FGFpTo2911r9tQDl%2BZFqnDqcY%3D&res
> erved=0
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references
2025-02-10 2:36 ` Peng Fan
@ 2025-02-10 15:48 ` Alexander Stein
2025-02-11 3:33 ` Peng Fan
0 siblings, 1 reply; 23+ messages in thread
From: Alexander Stein @ 2025-02-10 15:48 UTC (permalink / raw)
To: Peng Fan (OSS), Peng Fan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Am Montag, 10. Februar 2025, 03:36:48 CET schrieb Peng Fan:
> ********************
> Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie wissen, dass diese aus einer sicheren Quelle stammen und sicher sind. Leiten Sie die E-Mail im Zweifelsfall zur Prüfung an den IT-Helpdesk weiter.
> Attention external email: Open attachments and links only if you know that they are from a secure source and are safe. In doubt forward the email to the IT-Helpdesk to check it.
> ********************
>
> > Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-
> > controller references
> >
> > Hi Peng,
> >
> > Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan:
> > > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote:
> > > >Mark ocotp as a access-controller and add references on peripherals
> > > >which can be disabled (fused).
> > >
> > > I am not sure whether gpcv2 changes should be included in this
> > > patchset or not. Just add access-controller for fused IP will not work.
> >
> > Well, I was able to successfully boot a i.MX8M Nano DualLite.
> >
> > > i.MX8M BLK-CTRL/GPC will hang if the related power domain is still
> > > touched by kernel. The pgc can't power up/down because clock is
> > gated.
> >
> > Well, with GPU node disabled, no one should enable the power domain.
> > But to be on the safe side I would also add access-controllers to the
> > corresponding power domains as well.
> >
> > > This comment also apply to i.MX8MM/P.
> >
> > Sure. Do you have any information what is actually disabled by those
> > fused?
> > It seems it's the IP and their power domains. Anything else?
>
> In NXP downstream there is a patch for drivers/pmdomain/imx/imx8m-blk-ctrl.c
>
> soc: imx8m-blk-ctrl: Support fused modules
>
> For fused module, its pgc can't power up/down and clock is gated.
> Because imx8m-blk-ctrl driver will pm_runtime_get_sync/pm_runtime_put
> all power domains during suspend/resume. So we have to remove the
> pgc and clock of fused module from blk-ctrl DTS node.
> Update the driver to support such case.
>
> But this patch also needs U-Boot to update device tree nodes,
> I recalled that U-Boot will remove gpc nodes, but not update blk-ctrl nodes.
Does it work, if we add the access-controller as well for pgc_gpu3d
on imx8mp? There is nothing in blk-ctrl AFAICS. But for VPU there is.
Which clock needs to be removed there in case g1 is disabled?
Best regards,
Alexander
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references
2025-02-10 15:48 ` Alexander Stein
@ 2025-02-11 3:33 ` Peng Fan
2025-02-12 8:10 ` Alexander Stein
0 siblings, 1 reply; 23+ messages in thread
From: Peng Fan @ 2025-02-11 3:33 UTC (permalink / raw)
To: Alexander Stein
Cc: Peng Fan, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
On Mon, Feb 10, 2025 at 04:48:56PM +0100, Alexander Stein wrote:
>Am Montag, 10. Februar 2025, 03:36:48 CET schrieb Peng Fan:
>> ********************
>> Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie wissen, dass diese aus einer sicheren Quelle stammen und sicher sind. Leiten Sie die E-Mail im Zweifelsfall zur Prüfung an den IT-Helpdesk weiter.
>> Attention external email: Open attachments and links only if you know that they are from a secure source and are safe. In doubt forward the email to the IT-Helpdesk to check it.
>> ********************
>>
>> > Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-
>> > controller references
>> >
>> > Hi Peng,
>> >
>> > Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan:
>> > > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote:
>> > > >Mark ocotp as a access-controller and add references on peripherals
>> > > >which can be disabled (fused).
>> > >
>> > > I am not sure whether gpcv2 changes should be included in this
>> > > patchset or not. Just add access-controller for fused IP will not work.
>> >
>> > Well, I was able to successfully boot a i.MX8M Nano DualLite.
>> >
>> > > i.MX8M BLK-CTRL/GPC will hang if the related power domain is still
>> > > touched by kernel. The pgc can't power up/down because clock is
>> > gated.
>> >
>> > Well, with GPU node disabled, no one should enable the power domain.
>> > But to be on the safe side I would also add access-controllers to the
>> > corresponding power domains as well.
>> >
>> > > This comment also apply to i.MX8MM/P.
>> >
>> > Sure. Do you have any information what is actually disabled by those
>> > fused?
>> > It seems it's the IP and their power domains. Anything else?
>>
>> In NXP downstream there is a patch for drivers/pmdomain/imx/imx8m-blk-ctrl.c
>>
>> soc: imx8m-blk-ctrl: Support fused modules
>>
>> For fused module, its pgc can't power up/down and clock is gated.
>> Because imx8m-blk-ctrl driver will pm_runtime_get_sync/pm_runtime_put
>> all power domains during suspend/resume. So we have to remove the
>> pgc and clock of fused module from blk-ctrl DTS node.
>> Update the driver to support such case.
>>
>> But this patch also needs U-Boot to update device tree nodes,
>> I recalled that U-Boot will remove gpc nodes, but not update blk-ctrl nodes.
>
>Does it work, if we add the access-controller as well for pgc_gpu3d
>on imx8mp? There is nothing in blk-ctrl AFAICS. But for VPU there is.
Adding access-controller under pgc_gpu node will not make fwdevlink
work for the pgc_gpu nodes. It does not have compatible, and device
is created by gpcv2 driver using platform_device_alloc. Same to vpu.
>Which clock needs to be removed there in case g1 is disabled?
Take i.MX8MP VC8000E as example, the vpumix blk ctrl, the vc8000e
reference under vpumix blkctrl should be removed, including pd and clock.
So for non-blkctrl nodes, it is fine to use access-controller and rely
on fwdelink to defer probe. But for blk ctrl nodes, it will not work.
For pgc nodes, it may or may not matter, not very sure for now.
For blk ctrl nodes, we need provide a generic API saying
access_control_check or directly using nvmem API.
Regards,
Peng
>
>Best regards,
>Alexander
>--
>TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
>Amtsgericht München, HRB 105018
>Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
>http://www.tq-group.com/
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references
2025-02-11 3:33 ` Peng Fan
@ 2025-02-12 8:10 ` Alexander Stein
2025-02-12 8:22 ` Peng Fan
0 siblings, 1 reply; 23+ messages in thread
From: Alexander Stein @ 2025-02-12 8:10 UTC (permalink / raw)
To: Peng Fan
Cc: Peng Fan, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Am Dienstag, 11. Februar 2025, 04:33:41 CET schrieb Peng Fan:
>
> On Mon, Feb 10, 2025 at 04:48:56PM +0100, Alexander Stein wrote:
> >Am Montag, 10. Februar 2025, 03:36:48 CET schrieb Peng Fan:
> >> > Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-
> >> > controller references
> >> >
> >> > Hi Peng,
> >> >
> >> > Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan:
> >> > > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote:
> >> > > >Mark ocotp as a access-controller and add references on peripherals
> >> > > >which can be disabled (fused).
> >> > >
> >> > > I am not sure whether gpcv2 changes should be included in this
> >> > > patchset or not. Just add access-controller for fused IP will not work.
> >> >
> >> > Well, I was able to successfully boot a i.MX8M Nano DualLite.
> >> >
> >> > > i.MX8M BLK-CTRL/GPC will hang if the related power domain is still
> >> > > touched by kernel. The pgc can't power up/down because clock is
> >> > gated.
> >> >
> >> > Well, with GPU node disabled, no one should enable the power domain.
> >> > But to be on the safe side I would also add access-controllers to the
> >> > corresponding power domains as well.
> >> >
> >> > > This comment also apply to i.MX8MM/P.
> >> >
> >> > Sure. Do you have any information what is actually disabled by those
> >> > fused?
> >> > It seems it's the IP and their power domains. Anything else?
> >>
> >> In NXP downstream there is a patch for drivers/pmdomain/imx/imx8m-blk-ctrl.c
> >>
> >> soc: imx8m-blk-ctrl: Support fused modules
> >>
> >> For fused module, its pgc can't power up/down and clock is gated.
> >> Because imx8m-blk-ctrl driver will pm_runtime_get_sync/pm_runtime_put
> >> all power domains during suspend/resume. So we have to remove the
> >> pgc and clock of fused module from blk-ctrl DTS node.
> >> Update the driver to support such case.
> >>
> >> But this patch also needs U-Boot to update device tree nodes,
> >> I recalled that U-Boot will remove gpc nodes, but not update blk-ctrl nodes.
> >
> >Does it work, if we add the access-controller as well for pgc_gpu3d
> >on imx8mp? There is nothing in blk-ctrl AFAICS. But for VPU there is.
>
> Adding access-controller under pgc_gpu node will not make fwdevlink
> work for the pgc_gpu nodes. It does not have compatible, and device
> is created by gpcv2 driver using platform_device_alloc. Same to vpu.
>
> >Which clock needs to be removed there in case g1 is disabled?
>
> Take i.MX8MP VC8000E as example, the vpumix blk ctrl, the vc8000e
> reference under vpumix blkctrl should be removed, including pd and clock.
Wait, so you want to remove the last entry from these properties?
> clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
> <&clk IMX8MP_CLK_VPU_G2_ROOT>,
> <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
> clock-names = "g1", "g2", "vc8000e";
This violates the DT binding.
> So for non-blkctrl nodes, it is fine to use access-controller and rely
> on fwdelink to defer probe. But for blk ctrl nodes, it will not work.
>
> For pgc nodes, it may or may not matter, not very sure for now.
>
> For blk ctrl nodes, we need provide a generic API saying
> access_control_check or directly using nvmem API.
Reading access-controllers.yaml this should still be feasible for
providing the necessary information.
But I'm note sure where to implement this. In e.g. imx-ocotp would be a very
SoC-specific API.
Best regards,
Alexander
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references
2025-02-12 8:10 ` Alexander Stein
@ 2025-02-12 8:22 ` Peng Fan
0 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2025-02-12 8:22 UTC (permalink / raw)
To: Alexander Stein, Peng Fan (OSS)
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-
> controller references
>
> Am Dienstag, 11. Februar 2025, 04:33:41 CET schrieb Peng Fan:
> >
> > On Mon, Feb 10, 2025 at 04:48:56PM +0100, Alexander Stein wrote:
> > >Am Montag, 10. Februar 2025, 03:36:48 CET schrieb Peng Fan:
> > >> > Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access-
> > >> > controller references
> > >> >
> > >> > Hi Peng,
> > >> >
> > >> > Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan:
> > >> > > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein
> wrote:
> > >> > > >Mark ocotp as a access-controller and add references on
> > >> > > >peripherals which can be disabled (fused).
> > >> > >
> > >> > > I am not sure whether gpcv2 changes should be included in
> this
> > >> > > patchset or not. Just add access-controller for fused IP will not
> work.
> > >> >
> > >> > Well, I was able to successfully boot a i.MX8M Nano DualLite.
> > >> >
> > >> > > i.MX8M BLK-CTRL/GPC will hang if the related power domain is
> > >> > > still touched by kernel. The pgc can't power up/down because
> > >> > > clock is
> > >> > gated.
> > >> >
> > >> > Well, with GPU node disabled, no one should enable the power
> domain.
> > >> > But to be on the safe side I would also add access-controllers to
> > >> > the corresponding power domains as well.
> > >> >
> > >> > > This comment also apply to i.MX8MM/P.
> > >> >
> > >> > Sure. Do you have any information what is actually disabled by
> > >> > those fused?
> > >> > It seems it's the IP and their power domains. Anything else?
> > >>
> > >> In NXP downstream there is a patch for
> > >> drivers/pmdomain/imx/imx8m-blk-ctrl.c
> > >>
> > >> soc: imx8m-blk-ctrl: Support fused modules
> > >>
> > >> For fused module, its pgc can't power up/down and clock is
> gated.
> > >> Because imx8m-blk-ctrl driver will
> pm_runtime_get_sync/pm_runtime_put
> > >> all power domains during suspend/resume. So we have to
> remove the
> > >> pgc and clock of fused module from blk-ctrl DTS node.
> > >> Update the driver to support such case.
> > >>
> > >> But this patch also needs U-Boot to update device tree nodes, I
> > >> recalled that U-Boot will remove gpc nodes, but not update blk-
> ctrl nodes.
> > >
> > >Does it work, if we add the access-controller as well for pgc_gpu3d
> > >on imx8mp? There is nothing in blk-ctrl AFAICS. But for VPU there is.
> >
> > Adding access-controller under pgc_gpu node will not make
> fwdevlink
> > work for the pgc_gpu nodes. It does not have compatible, and device
> is
> > created by gpcv2 driver using platform_device_alloc. Same to vpu.
> >
> > >Which clock needs to be removed there in case g1 is disabled?
> >
> > Take i.MX8MP VC8000E as example, the vpumix blk ctrl, the vc8000e
> > reference under vpumix blkctrl should be removed, including pd and
> clock.
>
> Wait, so you want to remove the last entry from these properties?
>
> > clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
> > <&clk IMX8MP_CLK_VPU_G2_ROOT>,
> > <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
> > clock-names = "g1", "g2", "vc8000e";
>
> This violates the DT binding.
Not sure whether dt bindings should be different for one SoC
that some modules maybe fused out that not usable. Actually
this is different SoC per my understanding.
Without changing the binding, the idea I am thinking
is to add nvmem = <&ocotp X>, <& ocotp Y>, xxxx; for
the node. Then driver could check nvmem to see
whether module avaibable.
But for pgc, we still need the pd available from sw view,
otherwise blk ctrl may not probe because of
fwdevlink.
Regards,
Peng
>
> > So for non-blkctrl nodes, it is fine to use access-controller and rely
> > on fwdelink to defer probe. But for blk ctrl nodes, it will not work.
> >
> > For pgc nodes, it may or may not matter, not very sure for now.
> >
> > For blk ctrl nodes, we need provide a generic API saying
> > access_control_check or directly using nvmem API.
>
> Reading access-controllers.yaml this should still be feasible for
> providing the necessary information.
> But I'm note sure where to implement this. In e.g. imx-ocotp would be
> a very SoC-specific API.
>
> Best regards,
> Alexander
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld,
> Germany Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> www.tq-
> group.com%2F&data=05%7C02%7Cpeng.fan%40nxp.com%7Ccb387da
> 6989845e6bee608dd4b3ccd2a%7C686ea1d3bc2b4c6fa92cd99c5c301
> 635%7C0%7C0%7C638749446703427130%7CUnknown%7CTWFpbGZ
> sb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW
> 4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=d
> OARjpfOaGqV2GNJ9TPiUs7qd703QPOzjUiFFQMRX0s%3D&reserved=0
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 05/10] arm64: dts: imx8mp: Add i.MX8M Plus OCOTP disable fuse definitions
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
` (3 preceding siblings ...)
2025-02-07 8:36 ` [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 15:23 ` Frank Li
2025-02-07 8:36 ` [PATCH v2 06/10] arm64: dts: imx8mp: Add access-controller references Alexander Stein
` (4 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel
These definitions define the location of corresponding disable bits
in OCOTP peripheral.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8mp-ocotp.h | 42 ++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-ocotp.h
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mp-ocotp.h
new file mode 100644
index 0000000000000..c9f49c61f3656
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-ocotp.h
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+#ifndef __DTS_IMX8MP_OCOTP_H
+#define __DTS_IMX8MP_OCOTP_H
+
+/*
+ * The OCOTP is a tuple of
+ * <fuse_addr fuse_bit_offset>
+ */
+
+#define IMX8MP_OCOTP_M7_DISABLE 16 21
+#define IMX8MP_OCOTP_VPU_G1_DISABLE 16 24
+#define IMX8MP_OCOTP_VPU_G2_DISABLE 16 25
+#define IMX8MP_OCOTP_CAN_DISABLE 16 28
+#define IMX8MP_OCOTP_CAN_FD_DISABLE 16 29
+#define IMX8MP_OCOTP_VPU_VC8000E_DISABLE 16 30
+#define IMX8MP_OCOTP_IMG_ISP1_DISABLE 20 0
+#define IMX8MP_OCOTP_IMG_ISP2_DISABLE 20 1
+#define IMX8MP_OCOTP_IMG_DEWARP_DISABLE 20 2
+#define IMX8MP_OCOTP_NPU_DISABLE 20 3
+#define IMX8MP_OCOTP_AUDIO_PROCESSOR_DISABLE 20 4
+#define IMX8MP_OCOTP_ASRC_DISABLE 20 5
+#define IMX8MP_OCOTP_GPU2_DISABLE 20 6
+#define IMX8MP_OCOTP_GPU3_DISABLE 20 7
+#define IMX8MP_OCOTP_USB1_DISABLE 20 8
+#define IMX8MP_OCOTP_USB2_DISABLE 20 9
+#define IMX8MP_OCOTP_PCIE1_DISABLE 20 11
+#define IMX8MP_OCOTP_ENET1_DISABLE 20 13
+#define IMX8MP_OCOTP_ENET2_DISABLE 20 14
+#define IMX8MP_OCOTP_MIPI_CSI1_DISABLE 20 15
+#define IMX8MP_OCOTP_MIPI_CSI2_DISABLE 20 16
+#define IMX8MP_OCOTP_MIPI_DSI1_DISABLE 20 17
+#define IMX8MP_OCOTP_LVDS1_DISABLE 20 19
+#define IMX8MP_OCOTP_LVDS2_DISABLE 20 20
+#define IMX8MP_OCOTP_EARC_RX_DISABLE 20 30
+
+#endif /* __DTS_IMX8MP_OCOTP_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 05/10] arm64: dts: imx8mp: Add i.MX8M Plus OCOTP disable fuse definitions
2025-02-07 8:36 ` [PATCH v2 05/10] arm64: dts: imx8mp: Add i.MX8M Plus OCOTP disable fuse definitions Alexander Stein
@ 2025-02-07 15:23 ` Frank Li
0 siblings, 0 replies; 23+ messages in thread
From: Frank Li @ 2025-02-07 15:23 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree, imx, linux-arm-kernel,
linux-kernel
On Fri, Feb 07, 2025 at 09:36:10AM +0100, Alexander Stein wrote:
> These definitions define the location of corresponding disable bits
> in OCOTP peripheral.
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp-ocotp.h | 42 ++++++++++++++++++++
> 1 file changed, 42 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-ocotp.h
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mp-ocotp.h
> new file mode 100644
> index 0000000000000..c9f49c61f3656
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-ocotp.h
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
> +/*
> + * Copyright (c) 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
> + * D-82229 Seefeld, Germany.
> + * Author: Alexander Stein
> + */
> +
> +#ifndef __DTS_IMX8MP_OCOTP_H
> +#define __DTS_IMX8MP_OCOTP_H
> +
> +/*
> + * The OCOTP is a tuple of
> + * <fuse_addr fuse_bit_offset>
> + */
> +
> +#define IMX8MP_OCOTP_M7_DISABLE 16 21
> +#define IMX8MP_OCOTP_VPU_G1_DISABLE 16 24
> +#define IMX8MP_OCOTP_VPU_G2_DISABLE 16 25
> +#define IMX8MP_OCOTP_CAN_DISABLE 16 28
> +#define IMX8MP_OCOTP_CAN_FD_DISABLE 16 29
> +#define IMX8MP_OCOTP_VPU_VC8000E_DISABLE 16 30
> +#define IMX8MP_OCOTP_IMG_ISP1_DISABLE 20 0
> +#define IMX8MP_OCOTP_IMG_ISP2_DISABLE 20 1
> +#define IMX8MP_OCOTP_IMG_DEWARP_DISABLE 20 2
> +#define IMX8MP_OCOTP_NPU_DISABLE 20 3
> +#define IMX8MP_OCOTP_AUDIO_PROCESSOR_DISABLE 20 4
> +#define IMX8MP_OCOTP_ASRC_DISABLE 20 5
> +#define IMX8MP_OCOTP_GPU2_DISABLE 20 6
> +#define IMX8MP_OCOTP_GPU3_DISABLE 20 7
> +#define IMX8MP_OCOTP_USB1_DISABLE 20 8
> +#define IMX8MP_OCOTP_USB2_DISABLE 20 9
> +#define IMX8MP_OCOTP_PCIE1_DISABLE 20 11
> +#define IMX8MP_OCOTP_ENET1_DISABLE 20 13
> +#define IMX8MP_OCOTP_ENET2_DISABLE 20 14
> +#define IMX8MP_OCOTP_MIPI_CSI1_DISABLE 20 15
> +#define IMX8MP_OCOTP_MIPI_CSI2_DISABLE 20 16
> +#define IMX8MP_OCOTP_MIPI_DSI1_DISABLE 20 17
> +#define IMX8MP_OCOTP_LVDS1_DISABLE 20 19
> +#define IMX8MP_OCOTP_LVDS2_DISABLE 20 20
> +#define IMX8MP_OCOTP_EARC_RX_DISABLE 20 30
> +
> +#endif /* __DTS_IMX8MP_OCOTP_H */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 06/10] arm64: dts: imx8mp: Add access-controller references
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
` (4 preceding siblings ...)
2025-02-07 8:36 ` [PATCH v2 05/10] arm64: dts: imx8mp: Add i.MX8M Plus OCOTP disable fuse definitions Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 8:36 ` [PATCH v2 07/10] arm64: dts: imx8mm: Add i.MX8M Mini OCOTP disable fuse definitions Alexander Stein
` (3 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel
Mark ocotp as a access-controller and add references on peripherals
which can be disabled (fused).
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 66f7988271493..ee1cdfb660cf3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
+#include "imx8mp-ocotp.h"
#include "imx8mp-pinfunc.h"
/ {
@@ -670,6 +671,7 @@ ocotp: efuse@30350000 {
/* For nvmem subnodes */
#address-cells = <1>;
#size-cells = <1>;
+ #access-controller-cells = <2>;
/*
* The register address below maps to the MX8M
@@ -1137,6 +1139,7 @@ flexcan1: can@308c0000 {
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 4>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_CAN_DISABLE>;
status = "disabled";
};
@@ -1152,6 +1155,7 @@ flexcan2: can@308d0000 {
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 5>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_CAN_DISABLE>;
status = "disabled";
};
};
@@ -1371,6 +1375,7 @@ fec: ethernet@30be0000 {
nvmem-cells = <ð_mac1>;
nvmem-cell-names = "mac-address";
fsl,stop-mode = <&gpr 0x10 3>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_ENET1_DISABLE>;
status = "disabled";
};
@@ -1395,6 +1400,7 @@ eqos: ethernet@30bf0000 {
nvmem-cells = <ð_mac2>;
nvmem-cell-names = "mac-address";
intf_mode = <&gpr 0x4>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_ENET2_DISABLE>;
status = "disabled";
};
};
@@ -1526,6 +1532,7 @@ easrc: easrc@30c90000 {
firmware-name = "imx/easrc/easrc-imx8mn.bin";
fsl,asrc-rate = <8000>;
fsl,asrc-format = <2>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_ASRC_DISABLE>;
status = "disabled";
};
@@ -1582,6 +1589,7 @@ xcvr: xcvr@30cc0000 {
dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
dma-names = "rx", "tx";
resets = <&audio_blk_ctrl 0>;
+
status = "disabled";
};
};
@@ -1701,6 +1709,7 @@ isp_0: isp@32e10000 {
clock-names = "isp", "aclk", "hclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
fsl,blk-ctrl = <&media_blk_ctrl 0>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_IMG_ISP1_DISABLE>;
status = "disabled";
ports {
@@ -1723,6 +1732,7 @@ isp_1: isp@32e20000 {
clock-names = "isp", "aclk", "hclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
fsl,blk-ctrl = <&media_blk_ctrl 1>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_IMG_ISP2_DISABLE>;
status = "disabled";
ports {
@@ -1743,6 +1753,7 @@ dewarp: dwe@32e30000 {
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "axi", "ahb";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_IMG_DEWARP_DISABLE>;
};
mipi_csi_0: csi@32e40000 {
@@ -1760,6 +1771,7 @@ mipi_csi_0: csi@32e40000 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
<&clk IMX8MP_CLK_24M>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_MIPI_CSI1_DISABLE>;
status = "disabled";
ports {
@@ -1795,6 +1807,7 @@ mipi_csi_1: csi@32e50000 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
<&clk IMX8MP_CLK_24M>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_MIPI_CSI2_DISABLE>;
status = "disabled";
ports {
@@ -1829,6 +1842,7 @@ mipi_dsi: dsi@32e60000 {
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_MIPI_DSI1_DISABLE>;
status = "disabled";
ports {
@@ -1976,6 +1990,7 @@ ldb_from_lcdif2: endpoint {
};
port@1 {
+ access-controllers = <&ocotp IMX8MP_OCOTP_LVDS1_DISABLE>;
reg = <1>;
ldb_lvds_ch0: endpoint {
@@ -1983,6 +1998,7 @@ ldb_lvds_ch0: endpoint {
};
port@2 {
+ access-controllers = <&ocotp IMX8MP_OCOTP_LVDS2_DISABLE>;
reg = <2>;
ldb_lvds_ch1: endpoint {
@@ -2198,6 +2214,7 @@ pcie: pcie@33800000 {
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
+ access-controllers = <&ocotp IMX8MP_OCOTP_PCIE1_DISABLE>;
status = "disabled";
};
@@ -2227,6 +2244,7 @@ pcie_ep: pcie-ep@33800000 {
phy-names = "pcie-phy";
num-ib-windows = <4>;
num-ob-windows = <4>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_PCIE1_DISABLE>;
status = "disabled";
};
@@ -2245,6 +2263,7 @@ gpu3d: gpu@38000000 {
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <800000000>, <800000000>;
power-domains = <&pgc_gpu3d>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_GPU3_DISABLE>;
};
gpu2d: gpu@38008000 {
@@ -2259,6 +2278,7 @@ gpu2d: gpu@38008000 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <800000000>;
power-domains = <&pgc_gpu2d>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_GPU2_DISABLE>;
};
vpu_g1: video-codec@38300000 {
@@ -2270,6 +2290,7 @@ vpu_g1: video-codec@38300000 {
assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
assigned-clock-rates = <600000000>;
power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_VPU_G1_DISABLE>;
};
vpu_g2: video-codec@38310000 {
@@ -2281,6 +2302,7 @@ vpu_g2: video-codec@38310000 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_VPU_G2_DISABLE>;
};
vpumix_blk_ctrl: blk-ctrl@38330000 {
@@ -2313,6 +2335,7 @@ npu: npu@38500000 {
<&clk IMX8MP_CLK_ML_AHB>;
clock-names = "core", "shader", "bus", "reg";
power-domains = <&pgc_mlmix>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_NPU_DISABLE>;
};
gic: interrupt-controller@38800000 {
@@ -2362,6 +2385,7 @@ usb3_0: usb@32f10100 {
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
ranges;
+ access-controllers = <&ocotp IMX8MP_OCOTP_USB1_DISABLE>;
status = "disabled";
usb_dwc3_0: usb@38100000 {
@@ -2405,6 +2429,7 @@ usb3_1: usb@32f10108 {
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
ranges;
+ access-controllers = <&ocotp IMX8MP_OCOTP_USB2_DISABLE>;
status = "disabled";
usb_dwc3_1: usb@38200000 {
@@ -2430,6 +2455,7 @@ dsp: dsp@3b6e8000 {
mboxes = <&mu2 2 0>, <&mu2 2 1>,
<&mu2 3 0>, <&mu2 3 1>;
memory-region = <&dsp_reserved>;
+ access-controllers = <&ocotp IMX8MP_OCOTP_AUDIO_PROCESSOR_DISABLE>;
status = "disabled";
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 07/10] arm64: dts: imx8mm: Add i.MX8M Mini OCOTP disable fuse definitions
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
` (5 preceding siblings ...)
2025-02-07 8:36 ` [PATCH v2 06/10] arm64: dts: imx8mp: Add access-controller references Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 8:36 ` [PATCH v2 08/10] arm64: dts: imx8mm: Add access-controller references Alexander Stein
` (2 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel
These definitions define the location of corresponding disable bits
in OCOTP peripheral.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8mm-ocotp.h | 31 ++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-ocotp.h
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mm-ocotp.h
new file mode 100644
index 0000000000000..87698e7619262
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-ocotp.h
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+#ifndef __DTS_IMX8MM_OCOTP_H
+#define __DTS_IMX8MM_OCOTP_H
+
+/*
+ * The OCOTP is a tuple of
+ * <fuse_addr fuse_bit_offset>
+ */
+
+#define IMX8MM_OCOTP_M4_DISABLE 20 8
+#define IMX8MM_OCOTP_M4_MPU_DISABLE 20 9
+#define IMX8MM_OCOTP_M4_FPU_DISABLE 20 10
+#define IMX8MM_OCOTP_USB_OTG1_DISABLE 20 11
+#define IMX8MM_OCOTP_USB_OTG2_DISABLE 20 12
+#define IMX8MM_OCOTP_G1_DISABLE 20 18
+#define IMX8MM_OCOTP_G2_DISABLE 20 19
+#define IMX8MM_OCOTP_H1_DISABLE 20 20
+#define IMX8MM_OCOTP_GPU2D_DISABLE 20 21
+#define IMX8MM_OCOTP_PCIE1_DISABLE 20 22
+#define IMX8MM_OCOTP_GPU3D_DISABLE 20 24
+#define IMX8MM_OCOTP_MIPI_DSI_DISABLE 20 28
+#define IMX8MM_OCOTP_ENET_DISABLE 20 29
+#define IMX8MM_OCOTP_MIPI_CSI_DISABLE 20 30
+
+#endif /* __DTS_IMX8MM_OCOTP_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 08/10] arm64: dts: imx8mm: Add access-controller references
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
` (6 preceding siblings ...)
2025-02-07 8:36 ` [PATCH v2 07/10] arm64: dts: imx8mm: Add i.MX8M Mini OCOTP disable fuse definitions Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 8:36 ` [PATCH v2 09/10] arm64: dts: imx8mq: Add i.MX8M OCOTP disable fuse definitions Alexander Stein
2025-02-07 8:36 ` [PATCH v2 10/10] arm64: dts: imx8mq: Add access-controller references Alexander Stein
9 siblings, 0 replies; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel
Mark ocotp as a access-controller and add references on peripherals
which can be disabled (fused).
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1b147a09f6fe8..51472313b8294 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/thermal/thermal.h>
+#include "imx8mm-ocotp.h"
#include "imx8mm-pinfunc.h"
/ {
@@ -565,6 +566,7 @@ ocotp: efuse@30350000 {
/* For nvmem subnodes */
#address-cells = <1>;
#size-cells = <1>;
+ #access-controller-cells = <2>;
/*
* The register address below maps to the MX8M
@@ -1108,6 +1110,7 @@ fec1: ethernet@30be0000 {
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
fsl,stop-mode = <&gpr 0x10 3>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_ENET_DISABLE>;
status = "disabled";
};
@@ -1157,6 +1160,7 @@ mipi_dsi: dsi@32e10000 {
<&clk IMX8MM_CLK_24M>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_MIPI_DSI_DISABLE>;
status = "disabled";
ports {
@@ -1187,6 +1191,7 @@ csi: csi@32e20000 {
clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
clock-names = "mclk";
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_MIPI_CSI_DISABLE>;
status = "disabled";
port {
@@ -1270,6 +1275,7 @@ usbotg1: usb@32e40000 {
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_hsiomix>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_USB_OTG1_DISABLE>;
status = "disabled";
};
@@ -1290,6 +1296,7 @@ usbotg2: usb@32e50000 {
phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
power-domains = <&pgc_hsiomix>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_USB_OTG2_DISABLE>;
status = "disabled";
};
@@ -1375,6 +1382,7 @@ pcie0: pcie@33800000 {
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
+ access-controllers = <&ocotp IMX8MM_OCOTP_PCIE1_DISABLE>;
status = "disabled";
};
@@ -1401,6 +1409,7 @@ pcie0_ep: pcie-ep@33800000 {
phy-names = "pcie-phy";
num-ib-windows = <4>;
num-ob-windows = <4>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_PCIE1_DISABLE>;
status = "disabled";
};
@@ -1418,6 +1427,7 @@ gpu_3d: gpu@38000000 {
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-rates = <0>, <800000000>;
power-domains = <&pgc_gpu>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_GPU3D_DISABLE>;
};
gpu_2d: gpu@38008000 {
@@ -1433,6 +1443,7 @@ gpu_2d: gpu@38008000 {
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-rates = <0>, <800000000>;
power-domains = <&pgc_gpu>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_GPU2D_DISABLE>;
};
vpu_g1: video-codec@38300000 {
@@ -1441,6 +1452,7 @@ vpu_g1: video-codec@38300000 {
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_G1_DISABLE>;
};
vpu_g2: video-codec@38310000 {
@@ -1449,6 +1461,7 @@ vpu_g2: video-codec@38310000 {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_G2_DISABLE>;
};
vpu_blk_ctrl: blk-ctrl@38330000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 09/10] arm64: dts: imx8mq: Add i.MX8M OCOTP disable fuse definitions
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
` (7 preceding siblings ...)
2025-02-07 8:36 ` [PATCH v2 08/10] arm64: dts: imx8mm: Add access-controller references Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 15:24 ` Frank Li
2025-02-07 8:36 ` [PATCH v2 10/10] arm64: dts: imx8mq: Add access-controller references Alexander Stein
9 siblings, 1 reply; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel
These definitions define the location of corresponding disable bits
in OCOTP peripheral.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8mq-ocotp.h | 37 ++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-ocotp.h
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h
new file mode 100644
index 0000000000000..d991d57816264
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+#ifndef __DTS_IMX8MQ_OCOTP_H
+#define __DTS_IMX8MQ_OCOTP_H
+
+/*
+ * The OCOTP is a tuple of
+ * <fuse_addr fuse_bit_offset>
+ */
+
+#define IMX8MQ_OCOTP_M4_DISABLE 20 8
+#define IMX8MQ_OCOTP_M4_MPU_DISABLE 20 9
+#define IMX8MQ_OCOTP_M4_FPU_DISABLE 20 10
+#define IMX8MQ_OCOTP_USB_OTG1_DISABLE 20 11
+#define IMX8MQ_OCOTP_USB_OTG2_DISABLE 20 12
+#define IMX8MQ_OCOTP_DOLBY_DISABLE 20 13
+#define IMX8MQ_OCOTP_VP9_DISABLE 20 18
+#define IMX8MQ_OCOTP_HEVC_DISABLE 20 19
+#define IMX8MQ_OCOTP_AVC_DISABLE 20 20
+#define IMX8MQ_OCOTP_VPU_DISABLE 20 21
+#define IMX8MQ_OCOTP_PCIE1_DISABLE 20 22
+#define IMX8MQ_OCOTP_PCIE2_DISABLE 20 23
+#define IMX8MQ_OCOTP_GPU_DISABLE 20 24
+#define IMX8MQ_OCOTP_HDMI_DISABLE 20 25
+#define IMX8MQ_OCOTP_DC_DISABLE 20 26
+#define IMX8MQ_OCOTP_HDCP_DISABLE 20 27
+#define IMX8MQ_OCOTP_MIPI_DSI_DISABLE 20 28
+#define IMX8MQ_OCOTP_ENET_DISABLE 20 29
+#define IMX8MQ_OCOTP_MIPI_CSI1_DISABLE 20 30
+#define IMX8MQ_OCOTP_MIPI_CSI2_DISABLE 20 31
+
+#endif /* __DTS_IMX8MQ_OCOTP_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 09/10] arm64: dts: imx8mq: Add i.MX8M OCOTP disable fuse definitions
2025-02-07 8:36 ` [PATCH v2 09/10] arm64: dts: imx8mq: Add i.MX8M OCOTP disable fuse definitions Alexander Stein
@ 2025-02-07 15:24 ` Frank Li
0 siblings, 0 replies; 23+ messages in thread
From: Frank Li @ 2025-02-07 15:24 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla, devicetree, imx, linux-arm-kernel,
linux-kernel
On Fri, Feb 07, 2025 at 09:36:14AM +0100, Alexander Stein wrote:
> These definitions define the location of corresponding disable bits
> in OCOTP peripheral.
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> arch/arm64/boot/dts/freescale/imx8mq-ocotp.h | 37 ++++++++++++++++++++
> 1 file changed, 37 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-ocotp.h
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h
> new file mode 100644
> index 0000000000000..d991d57816264
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
> +/*
> + * Copyright (c) 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
> + * D-82229 Seefeld, Germany.
> + * Author: Alexander Stein
> + */
> +
> +#ifndef __DTS_IMX8MQ_OCOTP_H
> +#define __DTS_IMX8MQ_OCOTP_H
> +
> +/*
> + * The OCOTP is a tuple of
> + * <fuse_addr fuse_bit_offset>
> + */
> +
> +#define IMX8MQ_OCOTP_M4_DISABLE 20 8
> +#define IMX8MQ_OCOTP_M4_MPU_DISABLE 20 9
> +#define IMX8MQ_OCOTP_M4_FPU_DISABLE 20 10
> +#define IMX8MQ_OCOTP_USB_OTG1_DISABLE 20 11
> +#define IMX8MQ_OCOTP_USB_OTG2_DISABLE 20 12
> +#define IMX8MQ_OCOTP_DOLBY_DISABLE 20 13
> +#define IMX8MQ_OCOTP_VP9_DISABLE 20 18
> +#define IMX8MQ_OCOTP_HEVC_DISABLE 20 19
> +#define IMX8MQ_OCOTP_AVC_DISABLE 20 20
> +#define IMX8MQ_OCOTP_VPU_DISABLE 20 21
> +#define IMX8MQ_OCOTP_PCIE1_DISABLE 20 22
> +#define IMX8MQ_OCOTP_PCIE2_DISABLE 20 23
> +#define IMX8MQ_OCOTP_GPU_DISABLE 20 24
> +#define IMX8MQ_OCOTP_HDMI_DISABLE 20 25
> +#define IMX8MQ_OCOTP_DC_DISABLE 20 26
> +#define IMX8MQ_OCOTP_HDCP_DISABLE 20 27
> +#define IMX8MQ_OCOTP_MIPI_DSI_DISABLE 20 28
> +#define IMX8MQ_OCOTP_ENET_DISABLE 20 29
> +#define IMX8MQ_OCOTP_MIPI_CSI1_DISABLE 20 30
> +#define IMX8MQ_OCOTP_MIPI_CSI2_DISABLE 20 31
> +
> +#endif /* __DTS_IMX8MQ_OCOTP_H */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 10/10] arm64: dts: imx8mq: Add access-controller references
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
` (8 preceding siblings ...)
2025-02-07 8:36 ` [PATCH v2 09/10] arm64: dts: imx8mq: Add i.MX8M OCOTP disable fuse definitions Alexander Stein
@ 2025-02-07 8:36 ` Alexander Stein
2025-02-07 9:03 ` Alexander Stein
9 siblings, 1 reply; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 8:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: Alexander Stein, devicetree, imx, linux-arm-kernel, linux-kernel
Mark ocotp as a access-controller and add references on peripherals
which can be disabled (fused).
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index df8ba1d5391ae..95a40cccd46b9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interconnect/imx8mq.h>
+#include "imx8mq-ocotp.h"
#include "imx8mq-pinfunc.h"
/ {
@@ -1275,6 +1276,7 @@ mipi_dsi: dsi@30a00000 {
<&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
<&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
reset-names = "byte", "dpi", "esc", "pclk";
+ access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_DSI_DISABLE>;
status = "disabled";
ports {
@@ -1392,6 +1394,7 @@ mipi_csi1: csi@30a70000 {
fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
interconnect-names = "dram";
+ access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI1_DISABLE>;
status = "disabled";
ports {
@@ -1414,6 +1417,7 @@ csi1: csi@30a90000 {
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
clock-names = "mclk";
+ access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI1_DISABLE>;
status = "disabled";
port {
@@ -1444,6 +1448,7 @@ mipi_csi2: csi@30b60000 {
fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
interconnect-names = "dram";
+ access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI2_DISABLE>;
status = "disabled";
ports {
@@ -1466,6 +1471,7 @@ csi2: csi@30b80000 {
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
clock-names = "mclk";
+ access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI2_DISABLE>;
status = "disabled";
port {
@@ -1566,6 +1572,7 @@ fec1: ethernet@30be0000 {
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
+ access-controllers = <&ocotp IMX8MQ_OCOTP_ENET_DISABLE>;
status = "disabled";
};
};
@@ -1705,6 +1712,7 @@ gpu: gpu@38000000 {
<&clk IMX8MQ_GPU_PLL>;
assigned-clock-rates = <800000000>, <800000000>,
<800000000>, <800000000>, <0>;
+ access-controllers = <&ocotp IMX8MQ_OCOTP_GPU_DISABLE>;
power-domains = <&pgc_gpu>;
};
@@ -1725,6 +1733,7 @@ usb_dwc3_0: usb@38100000 {
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg1>;
snps,parkmode-disable-ss-quirk;
+ access-controllers = <&ocotp IMX8MQ_OCOTP_USB_OTG1_DISABLE>;
status = "disabled";
};
@@ -1757,6 +1766,7 @@ usb_dwc3_1: usb@38200000 {
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg2>;
snps,parkmode-disable-ss-quirk;
+ access-controllers = <&ocotp IMX8MQ_OCOTP_USB_OTG2_DISABLE>;
status = "disabled";
};
@@ -1778,6 +1788,7 @@ vpu_g1: video-codec@38300000 {
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
+ access-controllers = <&ocotp IMX8MQ_OCOTP_VPU_DISABLE>;
};
vpu_g2: video-codec@38310000 {
@@ -1786,6 +1797,7 @@ vpu_g2: video-codec@38310000 {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
+ access-controllers = <&ocotp IMX8MQ_OCOTP_VPU_DISABLE>;
};
vpu_blk_ctrl: blk-ctrl@38320000 {
@@ -1839,6 +1851,7 @@ pcie0: pcie@33800000 {
<&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
+ access-controllers = <&ocotp IMX8MQ_OCOTP_PCIE1_DISABLE>;
status = "disabled";
};
@@ -1882,6 +1895,7 @@ pcie1: pcie@33c00000 {
<&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
+ access-controllers = <&ocotp IMX8MQ_OCOTP_PCIE2_DISABLE>;
status = "disabled";
};
@@ -1916,6 +1930,7 @@ pcie1_ep: pcie-ep@33c00000 {
<10000000>;
num-ib-windows = <4>;
num-ob-windows = <4>;
+ access-controllers = <&ocotp IMX8MQ_OCOTP_PCIE2_DISABLE>;
status = "disabled";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 10/10] arm64: dts: imx8mq: Add access-controller references
2025-02-07 8:36 ` [PATCH v2 10/10] arm64: dts: imx8mq: Add access-controller references Alexander Stein
@ 2025-02-07 9:03 ` Alexander Stein
0 siblings, 0 replies; 23+ messages in thread
From: Alexander Stein @ 2025-02-07 9:03 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Srinivas Kandagatla
Cc: devicetree, imx, linux-arm-kernel, linux-kernel
Am Freitag, 7. Februar 2025, 09:36:15 CET schrieb Alexander Stein:
> Mark ocotp as a access-controller and add references on peripherals
> which can be disabled (fused).
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index df8ba1d5391ae..95a40cccd46b9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
I just noticed, I missed #access-controller-cells = <2>; for ocotp node.
Will add in next version.
Best regards,
Alexander
> @@ -12,6 +12,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/thermal/thermal.h>
> #include <dt-bindings/interconnect/imx8mq.h>
> +#include "imx8mq-ocotp.h"
> #include "imx8mq-pinfunc.h"
>
> / {
> @@ -1275,6 +1276,7 @@ mipi_dsi: dsi@30a00000 {
> <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
> <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
> reset-names = "byte", "dpi", "esc", "pclk";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_DSI_DISABLE>;
> status = "disabled";
>
> ports {
> @@ -1392,6 +1394,7 @@ mipi_csi1: csi@30a70000 {
> fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
> interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
> interconnect-names = "dram";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI1_DISABLE>;
> status = "disabled";
>
> ports {
> @@ -1414,6 +1417,7 @@ csi1: csi@30a90000 {
> interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
> clock-names = "mclk";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI1_DISABLE>;
> status = "disabled";
>
> port {
> @@ -1444,6 +1448,7 @@ mipi_csi2: csi@30b60000 {
> fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
> interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
> interconnect-names = "dram";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI2_DISABLE>;
> status = "disabled";
>
> ports {
> @@ -1466,6 +1471,7 @@ csi2: csi@30b80000 {
> interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
> clock-names = "mclk";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI2_DISABLE>;
> status = "disabled";
>
> port {
> @@ -1566,6 +1572,7 @@ fec1: ethernet@30be0000 {
> nvmem-cells = <&fec_mac_address>;
> nvmem-cell-names = "mac-address";
> fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_ENET_DISABLE>;
> status = "disabled";
> };
> };
> @@ -1705,6 +1712,7 @@ gpu: gpu@38000000 {
> <&clk IMX8MQ_GPU_PLL>;
> assigned-clock-rates = <800000000>, <800000000>,
> <800000000>, <800000000>, <0>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_GPU_DISABLE>;
> power-domains = <&pgc_gpu>;
> };
>
> @@ -1725,6 +1733,7 @@ usb_dwc3_0: usb@38100000 {
> phy-names = "usb2-phy", "usb3-phy";
> power-domains = <&pgc_otg1>;
> snps,parkmode-disable-ss-quirk;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_USB_OTG1_DISABLE>;
> status = "disabled";
> };
>
> @@ -1757,6 +1766,7 @@ usb_dwc3_1: usb@38200000 {
> phy-names = "usb2-phy", "usb3-phy";
> power-domains = <&pgc_otg2>;
> snps,parkmode-disable-ss-quirk;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_USB_OTG2_DISABLE>;
> status = "disabled";
> };
>
> @@ -1778,6 +1788,7 @@ vpu_g1: video-codec@38300000 {
> interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_VPU_DISABLE>;
> };
>
> vpu_g2: video-codec@38310000 {
> @@ -1786,6 +1797,7 @@ vpu_g2: video-codec@38310000 {
> interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_VPU_DISABLE>;
> };
>
> vpu_blk_ctrl: blk-ctrl@38320000 {
> @@ -1839,6 +1851,7 @@ pcie0: pcie@33800000 {
> <&clk IMX8MQ_SYS1_PLL_80M>;
> assigned-clock-rates = <250000000>, <100000000>,
> <10000000>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_PCIE1_DISABLE>;
> status = "disabled";
> };
>
> @@ -1882,6 +1895,7 @@ pcie1: pcie@33c00000 {
> <&clk IMX8MQ_SYS1_PLL_80M>;
> assigned-clock-rates = <250000000>, <100000000>,
> <10000000>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_PCIE2_DISABLE>;
> status = "disabled";
> };
>
> @@ -1916,6 +1930,7 @@ pcie1_ep: pcie-ep@33c00000 {
> <10000000>;
> num-ib-windows = <4>;
> num-ob-windows = <4>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_PCIE2_DISABLE>;
> status = "disabled";
> };
>
>
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
^ permalink raw reply [flat|nested] 23+ messages in thread