Re: [PATCH 8/8] media: imx-mipi-csis: Initial support for multiple output channels

[Alexander Stein <alexander.stein@ew.tq-group.com>]

Hi Laurent,

thanks for the patch.

Am Montag, 9. Juni 2025, 01:58:40 CEST schrieb Laurent Pinchart:
> Some CSIS instances feature more than one output channel. Parse the
> number of channels from the device tree, and update register dumps and
> event counters accordingly. Support for routing virtual channels and
> data types to output channels through the subdev internal routing API
> will come later.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
>  drivers/media/platform/nxp/imx-mipi-csis.c | 224 ++++++++++++++-------
>  1 file changed, 146 insertions(+), 78 deletions(-)
> 
> diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
> index 080e40837463..4cc358d93187 100644
> --- a/drivers/media/platform/nxp/imx-mipi-csis.c
> +++ b/drivers/media/platform/nxp/imx-mipi-csis.c
> @@ -98,12 +98,12 @@
>  #define MIPI_CSIS_INT_SRC_ODD_AFTER		BIT(28)
>  #define MIPI_CSIS_INT_SRC_ODD			(0x3 << 28)
>  #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA	(0xf << 28)

As a side note: I just noticed Bits 28-31 are only defined on i.MX7. They
are reserved on i.MX8M (Mini, Nano, Plus).

> -#define MIPI_CSIS_INT_SRC_FRAME_START		BIT(24)
> -#define MIPI_CSIS_INT_SRC_FRAME_END		BIT(20)
> +#define MIPI_CSIS_INT_SRC_FRAME_START(n)	BIT((n) + 24)
> +#define MIPI_CSIS_INT_SRC_FRAME_END(n)		BIT((n) + 20)
>  #define MIPI_CSIS_INT_SRC_ERR_SOT_HS(n)		BIT((n) + 16)
> -#define MIPI_CSIS_INT_SRC_ERR_LOST_FS		BIT(12)
> -#define MIPI_CSIS_INT_SRC_ERR_LOST_FE		BIT(8)
> -#define MIPI_CSIS_INT_SRC_ERR_OVER		BIT(4)
> +#define MIPI_CSIS_INT_SRC_ERR_LOST_FS(n)	BIT((n) + 12)
> +#define MIPI_CSIS_INT_SRC_ERR_LOST_FE(n)	BIT((n) + 8)
> +#define MIPI_CSIS_INT_SRC_ERR_OVER(n)		BIT((n) + 4)

Similar here. Only i.MX7 has the bits for CH1, CH2 and CH3 defined.

>  #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG		BIT(3)
>  #define MIPI_CSIS_INT_SRC_ERR_ECC		BIT(2)
>  #define MIPI_CSIS_INT_SRC_ERR_CRC		BIT(1)
> @@ -205,23 +205,23 @@
>  /* Debug control register */
>  #define MIPI_CSIS_DBG_CTRL			0xc0
>  #define MIPI_CSIS_DBG_INTR_MSK			0xc4
> -#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT	BIT(25)
> -#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE	BIT(24)
> -#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE	BIT(20)
> -#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME	BIT(16)
> -#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE		BIT(12)
> -#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS		BIT(8)
> -#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL	BIT(4)
> -#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE	BIT(0)
> +#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT		BIT(25)
> +#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE		BIT(24)
> +#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE(n)	BIT((n) + 20)
> +#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME(n)	BIT((n) + 16)
> +#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE(n)		BIT((n) + 12)
> +#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS(n)		BIT((n) + 8)
> +#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL(n)	BIT((n) + 4)
> +#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE(n)	BIT((n) + 0)
>  #define MIPI_CSIS_DBG_INTR_SRC			0xc8
> -#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT	BIT(25)
> -#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE	BIT(24)
> -#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE	BIT(20)
> -#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME	BIT(16)
> -#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE		BIT(12)
> -#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS		BIT(8)
> -#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL	BIT(4)
> -#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE	BIT(0)
> +#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT		BIT(25)
> +#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE		BIT(24)
> +#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(n)	BIT((n) + 20)
> +#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(n)	BIT((n) + 16)
> +#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(n)		BIT((n) + 12)
> +#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(n)		BIT((n) + 8)
> +#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(n)	BIT((n) + 4)
> +#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(n)	BIT((n) + 0)

Out of curiosity: Where do these bits come from? I can't find them in RM.

Best regards,
Alexander

> [snip]
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