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Mon, 29 Jul 2019 17:55:52 +0200 (CEST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Uwe =?ISO-8859-1?Q?Kleine=2DK=F6nig?= Subject: Re: [PATCH 4/6] pwm: sun4i: Add support for H6 PWM Date: Mon, 29 Jul 2019 17:55:52 +0200 Message-ID: <223488703.0I5IR7NXoI@jernej-laptop> In-Reply-To: <20190729064030.7uenld2kbof45zti@pengutronix.de> References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-5-jernej.skrabec@siol.net> <20190729064030.7uenld2kbof45zti@pengutronix.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190729_085556_711511_190D280D X-CRM114-Status: GOOD ( 17.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, mripard@kernel.org, wens@csie.org, robh+dt@kernel.org, thierry.reding@gmail.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Uwe, Dne ponedeljek, 29. julij 2019 ob 08:40:30 CEST je Uwe Kleine-K=F6nig = napisal(a): > On Fri, Jul 26, 2019 at 08:40:43PM +0200, Jernej Skrabec wrote: > > Now that sun4i PWM driver supports deasserting reset line and enabling > > bus clock, support for H6 PWM can be added. > > = > > Note that while H6 PWM has two channels, only first one is wired to > > output pin. Second channel is used as a clock source to companion AC200 > > chip which is bundled into same package. > > = > > Signed-off-by: Jernej Skrabec > > --- > > = > > drivers/pwm/pwm-sun4i.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > = > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 7d3ac3f2dc3f..9e0eca79ff88 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -331,6 +331,13 @@ static const struct sun4i_pwm_data > > sun4i_pwm_single_bypass =3D {> = > > .npwm =3D 1, > > = > > }; > > = > > +static const struct sun4i_pwm_data sun50i_pwm_dual_bypass_clk_rst =3D { > > + .has_bus_clock =3D true, > > + .has_prescaler_bypass =3D true, > > + .has_reset =3D true, > > + .npwm =3D 2, > > +}; > > + > > = > > static const struct of_device_id sun4i_pwm_dt_ids[] =3D { > > = > > { > > = > > .compatible =3D "allwinner,sun4i-a10-pwm", > > = > > @@ -347,6 +354,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[]= =3D > > { > > = > > }, { > > = > > .compatible =3D "allwinner,sun8i-h3-pwm", > > .data =3D &sun4i_pwm_single_bypass, > > = > > + }, { > > + .compatible =3D "allwinner,sun50i-h6-pwm", > > + .data =3D &sun50i_pwm_dual_bypass_clk_rst, > = > If you follow my suggestion for the two previous patches, you can just > use: > = > compatible =3D "allwinner,sun50i-h6-pwm", "allwinner,sun5i-a10s-pwm"; > = > and drop this patch. Maxime found out that it's not compatible with A10s due to difference in by= pass = bit, but yes, I know what you mean. Since H6 requires reset line and bus clock to be specified, it's not compat= ible = from DT binding side. New yaml based binding must somehow know that in orde= r = to be able to validate DT node, so it needs standalone compatible. However, = depending on conclusions of other discussions, this new compatible can be = associated with already available quirks structure or have it's own. Best regards, Jernej > = > Best regards > Uwe > = > > }, { > > = > > /* sentinel */ > > = > > }, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel