[PATCH 0/2] Fix a __clk_core_init parental issue

[PATCH 0/2] Fix a __clk_core_init parental issue

[Nicolas Frattaroli]

Mark and Alexander, please test to see if these patches resolve the
issues on your boards.

I expect the first patch to completely fix the problem on the Avenger96
(STM32MP1) board.

I'm less sure about the i.MX8MP board. I believe the second patch is
needed there, but I don't know for certain, as I don't have the hardware
to test.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Nicolas Frattaroli (2):
      clk: Disable CLK_OPS_PARENT_ENABLED parent only after CRITICAL check
      clk: imx8mp: Mark arm_a53_div as critical

 drivers/clk/clk.c            | 6 +++---
 drivers/clk/imx/clk-imx8mp.c | 4 +++-
 drivers/clk/imx/clk.h        | 4 ++++
 3 files changed, 10 insertions(+), 4 deletions(-)
---
base-commit: c099ccb60bc99900dd54ac22d7e68b8e56f15e4b
change-id: 20260128-ops-parent-enable-fix-65ee4977cbd3

Best regards,
-- 
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>

[PATCH 1/2] clk: Disable CLK_OPS_PARENT_ENABLED parent only after CRITICAL check

[Nicolas Frattaroli]

The call to clk_core_enable_lock done by __clk_core_init after checking
the clock flags for CLK_IS_CRITICAL enables the parent clock.

In Commit 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during
recalc"), the parent gets disabled before this check, if the flag
CLK_OPS_PARENT_ENABLED is set on the clock. This results in a situation
where critical clocks have their parent briefly disabled, which kills
the system.

Fix this by moving the balancing operation to after the CLK_IS_CRITICAL
check, which should resolve the problem.

Fixes: 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc")
Reported-by: Mark Brown <broonie@kernel.org>
Closes: https://lore.kernel.org/r/036da7ce-6487-4a6e-9b15-97c6d3bcdcec@sirena.org.uk/
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
 drivers/clk/clk.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 1b0f9d567f48..8f5ef9ce77d2 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -4056,9 +4056,6 @@ static int __clk_core_init(struct clk_core *core)
 		rate = 0;
 	core->rate = core->req_rate = rate;
 
-	if (core->flags & CLK_OPS_PARENT_ENABLE)
-		clk_core_disable_unprepare(core->parent);
-
 	/*
 	 * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
 	 * don't get accidentally disabled when walking the orphan tree and
@@ -4081,6 +4078,9 @@ static int __clk_core_init(struct clk_core *core)
 		}
 	}
 
+	if (core->flags & CLK_OPS_PARENT_ENABLE)
+		clk_core_disable_unprepare(core->parent);
+
 	clk_core_reparent_orphans_nolock();
 out:
 	clk_pm_runtime_put(core);

-- 
2.52.0

[PATCH 2/2] clk: imx8mp: Mark arm_a53_div as critical

[Nicolas Frattaroli]

It appears the i.MX8MP does not like when arm_a53_div, or rather the
parent it depends on, sys_pll2_500m, is briefly turned off during
__clk_core_init.

In the past, this clock driver could get away with not declaring the
clock as critical, as nothing ever fiddled with its parent that early
on. However, after Commit 669917676e93 ("clk: Respect
CLK_OPS_PARENT_ENABLE during recalc"), this changed.

In order to guarantee that it keeps its parent enabled during
__clk_core_init if it sets the flag CLK_OPS_PARENT_ENABLE, the clock
must be marked as critical.

Fixes: 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc")
Reported-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Closes: https://lore.kernel.org/r/6239343.lOV4Wx5bFT@steina-w/
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
 drivers/clk/imx/clk-imx8mp.c | 4 +++-
 drivers/clk/imx/clk.h        | 4 ++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index fe6dac70f1a1..ee10f845faff 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -655,7 +655,9 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4);
 	hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24);
 
-	hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
+	hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core_critical("arm_a53_div",
+								       imx8mp_a53_sels,
+								       ccm_base + 0x8000);
 	hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
 	hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
 	hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index aa5202f284f3..97cac1d623ca 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -454,6 +454,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
 	_imx8m_clk_hw_composite(name, parent_names, reg, \
 			IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
 
+#define imx8m_clk_hw_composite_core_critical(name, parent_names, reg)	\
+	_imx8m_clk_hw_composite(name, parent_names, reg, \
+			IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
+
 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
 	_imx8m_clk_hw_composite(name, parent_names, reg, \
 			IMX_COMPOSITE_FW_MANAGED, \

-- 
2.52.0

Re: [PATCH 0/2] Fix a __clk_core_init parental issue

[Mark Brown]

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On Wed, Jan 28, 2026 at 07:38:49PM +0100, Nicolas Frattaroli wrote:
> Mark and Alexander, please test to see if these patches resolve the
> issues on your boards.
> 
> I expect the first patch to completely fix the problem on the Avenger96
> (STM32MP1) board.

This gets further but still fails on Avenger96, looks like we've got
more clocks need work:

[    0.513739] __clk_core_init: enabling parent pll3_q for spi1_k
[    0.519521] __clk_core_init: disabling parent pll3_q for spi1_k
[    0.525489] __clk_core_init: enabling parent pll3_q for spi2_k
[    0.531311] __clk_core_init: disabling parent pll3_q for spi2_k
[    0.537275] __clk_core_init: enabling parent pll3_q for spi3_k
[    0.543101] __clk_core_init: disabling parent pll3_q for spi3_k
[    0.549066] __clk_core_init: enabling parent ck_hsi for spi4_k
[    0.554894] __clk_core_init: disabling parent ck�
U-Boot SPL 2023.07.02-dh-stm32mp1-dhcor-avenger96-20230727.02 (Jul 11 2023 - 15:20:44 +0000)

   https://lava.sirena.org.uk/scheduler/job/2413747#L593

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Re: [PATCH 0/2] Fix a __clk_core_init parental issue

[Alexander Stein]

Am Mittwoch, 28. Januar 2026, 21:17:09 CET schrieb Mark Brown:
> On Wed, Jan 28, 2026 at 07:38:49PM +0100, Nicolas Frattaroli wrote:
> > Mark and Alexander, please test to see if these patches resolve the
> > issues on your boards.
> > 
> > I expect the first patch to completely fix the problem on the Avenger96
> > (STM32MP1) board.
> 
> This gets further but still fails on Avenger96, looks like we've got
> more clocks need work:
> 
> [    0.513739] __clk_core_init: enabling parent pll3_q for spi1_k
> [    0.519521] __clk_core_init: disabling parent pll3_q for spi1_k
> [    0.525489] __clk_core_init: enabling parent pll3_q for spi2_k
> [    0.531311] __clk_core_init: disabling parent pll3_q for spi2_k
> [    0.537275] __clk_core_init: enabling parent pll3_q for spi3_k
> [    0.543101] __clk_core_init: disabling parent pll3_q for spi3_k
> [    0.549066] __clk_core_init: enabling parent ck_hsi for spi4_k
> [    0.554894] __clk_core_init: disabling parent ck�
> U-Boot SPL 2023.07.02-dh-stm32mp1-dhcor-avenger96-20230727.02 (Jul 11 2023 - 15:20:44 +0000)
> 
>    https://lava.sirena.org.uk/scheduler/job/2413747#L593
> 

I also got more clocks in the list, but it still hangs eventually:
[    1.453206] __clk_core_init: enabling parent audio_pll1_out for clkout1_sel
[    1.458095] __clk_core_init: disabling parent audio_pll1_out for clkout1_sel
[    1.464684] __clk_core_init: enabling parent audio_pll1_out for clkout2_sel
[    1.472174] __clk_core_init: disabling parent audio_pll1_out for clkout2_sel
[    1.478784] __clk_core_init: enabling parent sys_pll2_500m for arm_a53_div
[    1.485679] __clk_core_init: disabling parent sys_pll2_500m for arm_a53_div
[    1.492675] __clk_core_init: enabling parent sys_pll2_200m for m7_core
[    1.499233] __clk_core_init: disabling parent sys_pll2_200m for m7_core
[    1.505888] __clk_core_init: enabling parent osc_24m for ml_core
[    1.511924] __clk_core_init: disabling parent osc_24m for ml_core
[    1.518050] __clk_core_init: enabling parent osc_24m for gpu3d_core
[    1.524344] __clk_core_init: disabling parent osc_24m for gpu3d_core
[    1.530738] __clk_core_init: enabling parent osc_24m for gpu3d_shader_core
[    1.537646] __clk_core_init: disabling parent osc_24m for gpu3d_shader_core
[    1.544655] __clk_core_init: enabling parent osc_24m for gpu2d_core
[    1.550945] __clk_core_init: disabling parent osc_24m for gpu2d_core
[    1.557341] __clk_core_init: enabling parent osc_24m for audio_axi
[    1.563551] __clk_core_init: disabling parent osc_24m for audio_axi
[    1.569863] __clk_core_init: enabling parent sys_pll1_800m for hsio_axi
[    1.576507] __clk_core_init: disabling parent sys_pll1_800m for hsio_axi

Best regards,
Alexander
-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH 2/2] clk: imx8mp: Mark arm_a53_div as critical

[Daniel Baluta]

Hi Nicolas,

I've tested this series on i.MX8MP and unfortunately it doesn't fix the issue.
This is the serial console output: https://pastebin.com/dvJQ0HBy

We can talk privately and can help you test if you have debug patches.

Reverting:

669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc")

Makes everything work again.

thanks,
Daniel.

On Wed, Jan 28, 2026 at 8:40 PM Nicolas Frattaroli
<nicolas.frattaroli@collabora.com> wrote:
>
> It appears the i.MX8MP does not like when arm_a53_div, or rather the
> parent it depends on, sys_pll2_500m, is briefly turned off during
> __clk_core_init.
>
> In the past, this clock driver could get away with not declaring the
> clock as critical, as nothing ever fiddled with its parent that early
> on. However, after Commit 669917676e93 ("clk: Respect
> CLK_OPS_PARENT_ENABLE during recalc"), this changed.
>
> In order to guarantee that it keeps its parent enabled during
> __clk_core_init if it sets the flag CLK_OPS_PARENT_ENABLE, the clock
> must be marked as critical.
>
> Fixes: 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc")
> Reported-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Closes: https://lore.kernel.org/r/6239343.lOV4Wx5bFT@steina-w/
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> ---
>  drivers/clk/imx/clk-imx8mp.c | 4 +++-
>  drivers/clk/imx/clk.h        | 4 ++++
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index fe6dac70f1a1..ee10f845faff 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -655,7 +655,9 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>         hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4);
>         hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24);
>
> -       hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
> +       hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core_critical("arm_a53_div",
> +                                                                      imx8mp_a53_sels,
> +                                                                      ccm_base + 0x8000);
>         hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
>         hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
>         hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index aa5202f284f3..97cac1d623ca 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -454,6 +454,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
>         _imx8m_clk_hw_composite(name, parent_names, reg, \
>                         IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
>
> +#define imx8m_clk_hw_composite_core_critical(name, parent_names, reg)  \
> +       _imx8m_clk_hw_composite(name, parent_names, reg, \
> +                       IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
> +
>  #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
>         _imx8m_clk_hw_composite(name, parent_names, reg, \
>                         IMX_COMPOSITE_FW_MANAGED, \
>
> --
> 2.52.0
>
>

RE: [PATCH 2/2] clk: imx8mp: Mark arm_a53_div as critical

[Peng Fan]

> Subject: Re: [PATCH 2/2] clk: imx8mp: Mark arm_a53_div as critical
> 
> Reverting:
> 
> 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc")
> 
> Makes everything work again.

Same result at my side.

Regards
Peng.

> 
> thanks,
> Daniel.
> 
> On Wed, Jan 28, 2026 at 8:40 PM Nicolas Frattaroli
> <nicolas.frattaroli@collabora.com> wrote:
> >
> > It appears the i.MX8MP does not like when arm_a53_div, or rather
> the
> > parent it depends on, sys_pll2_500m, is briefly turned off during
> > __clk_core_init.
> >
> > In the past, this clock driver could get away with not declaring the
> > clock as critical, as nothing ever fiddled with its parent that early
> > on. However, after Commit 669917676e93 ("clk: Respect
> > CLK_OPS_PARENT_ENABLE during recalc"), this changed.
> >
> > In order to guarantee that it keeps its parent enabled during
> > __clk_core_init if it sets the flag CLK_OPS_PARENT_ENABLE, the clock
> > must be marked as critical.
> >
> > Fixes: 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE
> during
> > recalc")
> > Reported-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > Closes:
> >
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> lore
> > .kernel.org%2Fr%2F6239343.lOV4Wx5bFT%40steina-
> w%2F&data=05%7C02%7Cpeng
> > .fan%40nxp.com%7Cd94f80581364430cba2608de5f137ad4%7C686
> ea1d3bc2b4c6fa9
> >
> 2cd99c5c301635%7C0%7C0%7C639052734430562921%7CUnknown
> %7CTWFpbGZsb3d8ey
> >
> JFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIk
> FOIjoiTWFp
> >
> bCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=xOXu1JCLwpkzZi7p2
> yXoBYpSknlWnX
> > iQVCFyTlu8rtE%3D&reserved=0
> > Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> > ---
> >  drivers/clk/imx/clk-imx8mp.c | 4 +++-
> >  drivers/clk/imx/clk.h        | 4 ++++
> >  2 files changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp.c
> > b/drivers/clk/imx/clk-imx8mp.c index fe6dac70f1a1..ee10f845faff
> 100644
> > --- a/drivers/clk/imx/clk-imx8mp.c
> > +++ b/drivers/clk/imx/clk-imx8mp.c
> > @@ -655,7 +655,9 @@ static int imx8mp_clocks_probe(struct
> platform_device *pdev)
> >         hws[IMX8MP_CLK_CLKOUT2_DIV] =
> imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128,
> 16, 4);
> >         hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2",
> > "clkout2_div", anatop_base + 0x128, 24);
> >
> > -       hws[IMX8MP_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels,
> ccm_base + 0x8000);
> > +       hws[IMX8MP_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core_critical("arm_a53_div",
> > +                                                                      imx8mp_a53_sels,
> > +
> > + ccm_base + 0x8000);
> >         hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
> >         hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
> >         hws[IMX8MP_CLK_M7_CORE] =
> > imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels,
> ccm_base +
> > 0x8080); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> > index aa5202f284f3..97cac1d623ca 100644
> > --- a/drivers/clk/imx/clk.h
> > +++ b/drivers/clk/imx/clk.h
> > @@ -454,6 +454,10 @@ struct clk_hw
> *__imx8m_clk_hw_composite(const char *name,
> >         _imx8m_clk_hw_composite(name, parent_names, reg, \
> >                         IMX_COMPOSITE_CORE,
> > IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
> >
> > +#define imx8m_clk_hw_composite_core_critical(name,
> parent_names, reg)  \
> > +       _imx8m_clk_hw_composite(name, parent_names, reg, \
> > +                       IMX_COMPOSITE_CORE,
> > +IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
> > +
> >  #define imx8m_clk_hw_fw_managed_composite(name,
> parent_names, reg) \
> >         _imx8m_clk_hw_composite(name, parent_names, reg, \
> >                         IMX_COMPOSITE_FW_MANAGED, \
> >
> > --
> > 2.52.0
> >
> >

Re: [PATCH 1/2] clk: Disable CLK_OPS_PARENT_ENABLED parent only after CRITICAL check

[Daniel Baluta]

On Wed, Jan 28, 2026 at 8:39 PM Nicolas Frattaroli
<nicolas.frattaroli@collabora.com> wrote:
>
> The call to clk_core_enable_lock done by __clk_core_init after checking
> the clock flags for CLK_IS_CRITICAL enables the parent clock.
>
> In Commit 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during
> recalc"), the parent gets disabled before this check, if the flag
> CLK_OPS_PARENT_ENABLED is set on the clock. This results in a situation
> where critical clocks have their parent briefly disabled, which kills
> the system.
>
> Fix this by moving the balancing operation to after the CLK_IS_CRITICAL
> check, which should resolve the problem.
>
> Fixes: 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc")
> Reported-by: Mark Brown <broonie@kernel.org>
> Closes: https://lore.kernel.org/r/036da7ce-6487-4a6e-9b15-97c6d3bcdcec@sirena.org.uk/
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>

Hi Nicolas,

Would you consider please reverting faulty patch above as i.MX8mp is
still broken?

Re: [PATCH 1/2] clk: Disable CLK_OPS_PARENT_ENABLED parent only after CRITICAL check

[Mark Brown]

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On Tue, Feb 03, 2026 at 12:13:22PM +0200, Daniel Baluta wrote:

> Would you consider please reverting faulty patch above as i.MX8mp is
> still broken?

Stephen posted a revert yesterday:

   https://lore.kernel.org/r/20260203002439.1223213-1-sboyd@kernel.org

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