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Januar 2026, 21:17:09 CET schrieb Mark Brown: > On Wed, Jan 28, 2026 at 07:38:49PM +0100, Nicolas Frattaroli wrote: > > Mark and Alexander, please test to see if these patches resolve the > > issues on your boards. > >=20 > > I expect the first patch to completely fix the problem on the Avenger96 > > (STM32MP1) board. >=20 > This gets further but still fails on Avenger96, looks like we've got > more clocks need work: >=20 > [ 0.513739] __clk_core_init: enabling parent pll3_q for spi1_k > [ 0.519521] __clk_core_init: disabling parent pll3_q for spi1_k > [ 0.525489] __clk_core_init: enabling parent pll3_q for spi2_k > [ 0.531311] __clk_core_init: disabling parent pll3_q for spi2_k > [ 0.537275] __clk_core_init: enabling parent pll3_q for spi3_k > [ 0.543101] __clk_core_init: disabling parent pll3_q for spi3_k > [ 0.549066] __clk_core_init: enabling parent ck_hsi for spi4_k > [ 0.554894] __clk_core_init: disabling parent ck=EF=BF=BD > U-Boot SPL 2023.07.02-dh-stm32mp1-dhcor-avenger96-20230727.02 (Jul 11 202= 3 - 15:20:44 +0000) >=20 > https://lava.sirena.org.uk/scheduler/job/2413747#L593 >=20 I also got more clocks in the list, but it still hangs eventually: [ 1.453206] __clk_core_init: enabling parent audio_pll1_out for clkout1_= sel [ 1.458095] __clk_core_init: disabling parent audio_pll1_out for clkout1= _sel [ 1.464684] __clk_core_init: enabling parent audio_pll1_out for clkout2_= sel [ 1.472174] __clk_core_init: disabling parent audio_pll1_out for clkout2= _sel [ 1.478784] __clk_core_init: enabling parent sys_pll2_500m for arm_a53_d= iv [ 1.485679] __clk_core_init: disabling parent sys_pll2_500m for arm_a53_= div [ 1.492675] __clk_core_init: enabling parent sys_pll2_200m for m7_core [ 1.499233] __clk_core_init: disabling parent sys_pll2_200m for m7_core [ 1.505888] __clk_core_init: enabling parent osc_24m for ml_core [ 1.511924] __clk_core_init: disabling parent osc_24m for ml_core [ 1.518050] __clk_core_init: enabling parent osc_24m for gpu3d_core [ 1.524344] __clk_core_init: disabling parent osc_24m for gpu3d_core [ 1.530738] __clk_core_init: enabling parent osc_24m for gpu3d_shader_co= re [ 1.537646] __clk_core_init: disabling parent osc_24m for gpu3d_shader_c= ore [ 1.544655] __clk_core_init: enabling parent osc_24m for gpu2d_core [ 1.550945] __clk_core_init: disabling parent osc_24m for gpu2d_core [ 1.557341] __clk_core_init: enabling parent osc_24m for audio_axi [ 1.563551] __clk_core_init: disabling parent osc_24m for audio_axi [ 1.569863] __clk_core_init: enabling parent sys_pll1_800m for hsio_axi [ 1.576507] __clk_core_init: disabling parent sys_pll1_800m for hsio_axi Best regards, Alexander =2D-=20 TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, Germ= any Amtsgericht M=C3=BCnchen, HRB 105018 Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan Sch= neider http://www.tq-group.com/