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([2a02:ab88:3711:c80:e7a7:e025:f1a5:ef78]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5b83b82f308sm7200821a12.63.2024.08.07.10.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Aug 2024 10:28:37 -0700 (PDT) Message-ID: <225a94c3d0e8f70238aa9a486e7752ad6cb20283.camel@gmail.com> Subject: Re: [PATCH v1 08/10] arm64: dts: exynos: Add initial support for exynos8895 SoC From: David Virag To: Ivaylo Ivanov , Krzysztof Kozlowski , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Rob Herring Cc: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Date: Wed, 07 Aug 2024 19:29:51 +0200 In-Reply-To: <5274b8a1-b81c-3979-ed6c-3572f6a6cfc2@gmail.com> References: <20240807082843.352937-1-ivo.ivanov.ivanov1@gmail.com> <20240807082843.352937-9-ivo.ivanov.ivanov1@gmail.com> <5274b8a1-b81c-3979-ed6c-3572f6a6cfc2@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240807_102840_548684_70C739D5 X-CRM114-Status: GOOD ( 23.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2024-08-07 at 14:20 +0300, Ivaylo Ivanov wrote: >=20 > On 8/7/24 12:20, Krzysztof Kozlowski wrote: > > On 07/08/2024 10:28, ivo.ivanov.ivanov1@gmail.com=C2=A0wrote: > > > From: Ivaylo Ivanov [snip] > > >=20 > > > + > > > + timer { > > > + compatible =3D "arm,armv8-timer"; > > > + /* Hypervisor Virtual Timer interrupt is not > > > wired to GIC */ > > > + interrupts =3D > > | IRQ_TYPE_LEVEL_LOW)>, > > > + =C2=A0=C2=A0=C2=A0=C2=A0 > > | IRQ_TYPE_LEVEL_LOW)>, > > > + =C2=A0=C2=A0=C2=A0=C2=A0 > > | IRQ_TYPE_LEVEL_LOW)>, > > > + =C2=A0=C2=A0=C2=A0=C2=A0 > > | IRQ_TYPE_LEVEL_LOW)>; > > > + clock-frequency =3D <26000000>; > > Hm? I think this was explicitly disallowed. >=20 > It's weird. Without the clock-frequency property it fails early > during the >=20 > boot process and I can't get any logs from pstore or simple- > framebuffer. >=20 > Yet it's not set on similar platforms (exynos7885, autov9). Perhaps I >=20 > could alias the node and set it in the board device tree..? That > doesn't >=20 > sound right. This sounds like CNTFRQ_EL0 is not set properly by the firmware. Now, if I read the documentation properly, this can be only set from EL3, which in your case is... not easy. On my Galaxy A8 2018 (Exynos7885) I remember the old Android 8 bootloader not being able to boot mainline, but Android 9 bootloaders did. I did not take the time to check if it was related to this, but it is my guess. Your best bet is that maybe Samsung decided to fix this on the latest bootloader, and upgrading will fix it. (Though if it's already on an Android 9 based bootloader and it's still broken, my guess is a newer version won't fix it, but who knows) Or... Exynos8895 has a known bootrom vulnerability, you could force the SoC into USB Download mode, and use the exploit to boot into a patched bootloader. This is of course pretty tedious. Your only actually relistic choice is submitting without this line and manually adding it while actually using the phone (or making the chainloaded bootloader/boot wrapper add it). Not optimal, but it is what it is... Best Regards, David