[PATCH 19/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588-jaguar

Cristian Ciocaltea
2026-04-17T09:26:15Z

The board exposes the GPIO0_D3 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.

Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
index 5f5d89a33a4a..ad9809aaff7e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
@@ -279,7 +279,9 @@ &gpu {
&hdmi0 {
/* No CEC on Jaguar */
pinctrl-names = "default";
- pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>;
+ pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda
+ &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
status = "okay";
};

@@ -571,6 +573,12 @@ eth_reset: eth-reset {
};
};

+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
leds {
led1_pin: led1-pin {
rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;

--
2.53.0