Re: [PATCH v2] ARM: dts: bcm2711-rpi-cm4-io: Add rtc on a pinctrl-muxed i2c bus

["Uwe Kleine-König" <uwe@kleine-koenig.org>]

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Hello,

I used the wrong git wrapper so this patch appeared with the wrong 
sender address. If need be I can resend from the address used in the S-o-b.

On 12/9/21 19:18, Uwe Kleine-König wrote:
> From: Uwe Kleine-König <uwe@kleine-koenig.org>
> 
> The cm4-io board comes with an PCF85063. Add it to the device tree to make
> it usable. The i2c0 bus can use two different pinmux settings to use
> different pins. To keep the bus appearing on the usual pin pair (gpio0 +
> gpio1) use a pinctrl-muxed setting as the upstream dts does.
> 
> Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
> ---
>   arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts | 35 ++++++++++++++++++++++++
>   1 file changed, 35 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts
> index 19600b629be5..5ddad146b541 100644
> --- a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts
> +++ b/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts
> @@ -18,6 +18,41 @@ led-pwr {
>   			linux,default-trigger = "default-on";
>   		};
>   	};
> +
> +	i2c0mux {
> +		compatible = "i2c-mux-pinctrl";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		i2c-parent = <&i2c0>;
> +
> +		pinctrl-names = "i2c0", "i2c0-vc";
> +		pinctrl-0 = <&i2c0_gpio0>;
> +		pinctrl-1 = <&i2c0_gpio44>;
> +
> +		i2c@0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c@1 {
> +			reg = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			rtc@51 {
> +				/* Attention: An alarm resets the machine */
> +				compatible = "nxp,pcf85063";
> +				reg = <0x51>;
> +			};
> +		};
> +	};
> +};
> +
> +&i2c0 {
> +	/delete-property/ pinctrl-names;
> +	/delete-property/ pinctrl-0;
>   };
>   
>   &ddc0 {

Just some further information:

Cyril (who I talked to on irc) and I found that not only i2c0 can be 
used to access the gpio bus on pins 44/45 (as I did in v1) but that also 
&i2c1 can drive these pins. However similar to &i2c0, &i2c1 is used on 
pins 2/3 per default and so is also available on the default gpio header.

Also note that this is a breaking change, because overlays that added 
devices to &i2c0 before (expecting them to be accessed via gpio0/1) need 
to modify /i2c0mux/i2c@0 now instead of /soc/i2c@7e205000 (aka &i2c0).

Best regards
Uwe

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