Re: [PATCH net-next v2 07/10] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port

["Jernej Škrabec" <jernej.skrabec@gmail.com>]

Dne sreda, 13. avgust 2025 ob 16:55:37 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):
> From: Chen-Yu Tsai <wens@csie.org>
> 
> On the Radxa Cubie A5E board, the second Ethernet controller, aka the
> GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY
> uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to
> its reset pin.
> 
> Enable the second Ethernet port. Also fix up the label for the existing
> external PHY connected to the first Ethernet port. An enable delay for the
> PHY supply regulator is added to make sure the PHY's internal regulators
> are fully powered and the PHY is operational.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

> ---
> 
> Changes since v1:
> - Switch to generic (tx|rx)-internal-delay-ps properties
> - Add PHY regulator delay
> ---
>  .../dts/allwinner/sun55i-a527-cubie-a5e.dts   | 28 +++++++++++++++++--
>  1 file changed, 26 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> index d4cee2222104..e96a419faf21 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> @@ -14,6 +14,7 @@ / {
>  
>  	aliases {
>  		ethernet0 = &gmac0;
> +		ethernet1 = &gmac1;
>  		serial0 = &uart0;
>  	};
>  
> @@ -76,7 +77,7 @@ &ehci1 {
>  
>  &gmac0 {
>  	phy-mode = "rgmii-id";
> -	phy-handle = <&ext_rgmii_phy>;
> +	phy-handle = <&ext_rgmii0_phy>;
>  	phy-supply = <&reg_cldo3>;
>  
>  	allwinner,tx-delay-ps = <300>;
> @@ -85,13 +86,24 @@ &gmac0 {
>  	status = "okay";
>  };
>  
> +&gmac1 {
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ext_rgmii1_phy>;
> +	phy-supply = <&reg_cldo4>;
> +
> +	tx-internal-delay-ps = <300>;
> +	rx-internal-delay-ps = <400>;
> +
> +	status = "okay";
> +};
> +
>  &gpu {
>  	mali-supply = <&reg_dcdc2>;
>  	status = "okay";
>  };
>  
>  &mdio0 {
> -	ext_rgmii_phy: ethernet-phy@1 {
> +	ext_rgmii0_phy: ethernet-phy@1 {
>  		compatible = "ethernet-phy-ieee802.3-c22";
>  		reg = <1>;
>  		reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
> @@ -100,6 +112,16 @@ ext_rgmii_phy: ethernet-phy@1 {
>  	};
>  };
>  
> +&mdio1 {
> +	ext_rgmii1_phy: ethernet-phy@1 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <1>;
> +		reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */
> +		reset-assert-us = <10000>;
> +		reset-deassert-us = <150000>;
> +	};
> +};
> +
>  &mmc0 {
>  	vmmc-supply = <&reg_cldo3>;
>  	cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */
> @@ -240,6 +262,8 @@ reg_cldo4: cldo4 {
>  				regulator-min-microvolt = <3300000>;
>  				regulator-max-microvolt = <3300000>;
>  				regulator-name = "vcc-pj-phy";
> +				/* enough time for the PHY to fully power on */
> +				regulator-enable-ramp-delay = <150000>;
>  			};
>  
>  			reg_cpusldo: cpusldo {
>