From: "Heiko Stübner" <heiko@sntech.de>
To: Jonathan Cameron <jic23@kernel.org>,
Lars-Peter Clausen <lars@metafoo.de>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Andy Shevchenko <andy.shevchenko@gmail.com>,
Shreeya Patel <shreeya.patel@collabora.com>,
Simon Xue <xxm@rock-chips.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Quentin Schulz <foss+kernel@0leil.net>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
Quentin Schulz <quentin.schulz@theobroma-systems.com>,
Quentin Schulz <foss+kernel@0leil.net>
Subject: Re: [PATCH 2/3] iio: adc: rockchip_saradc: use mask for write_enable bitfield
Date: Fri, 23 Feb 2024 14:43:41 +0100 [thread overview]
Message-ID: <2385656.yKrmzQ4Hd0@diego> (raw)
In-Reply-To: <20240223-saradcv2-chan-mask-v1-2-84b06a0f623a@theobroma-systems.com>
Am Freitag, 23. Februar 2024, 13:45:22 CET schrieb Quentin Schulz:
> From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
>
> Some of the registers on the SARADCv2 have bits write protected except
> if another bit is set. This is usually done by having the lowest 16 bits
> store the data to write and the highest 16 bits specify which of the 16
> lowest bits should have their value written to the hardware block.
>
> The write_enable mask for the channel selection was incorrect because it
> was just the value shifted by 16 bits, which means it would only ever
> write bits and never clear them. So e.g. if someone starts a conversion
> on channel 5, the lowest 4 bits would be 0x5, then starts a conversion
> on channel 0, it would still be 5.
>
> Instead of shifting the value by 16 as the mask, let's use the OR'ing of
> the appropriate masks shifted by 16.
>
> Note that this is not an issue currently because the only SARADCv2
> currently supported has a reset defined in its Device Tree, that reset
> resets the SARADC controller before starting a conversion on a channel.
> However, this reset is handled as optional by the probe function and
> thus proper masking should be used in the event an SARADCv2 without a
> reset ever makes it upstream.
>
> Fixes: 757953f8ec69 ("iio: adc: rockchip_saradc: Add support for RK3588")
> Cc: Quentin Schulz <foss+kernel@0leil.net>
> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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next prev parent reply other threads:[~2024-02-23 13:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-23 12:45 [PATCH 0/3] iio: adc: rockchip_saradc: fix bitmasking and remove custom logic for getting reset Quentin Schulz
2024-02-23 12:45 ` [PATCH 1/3] iio: adc: rockchip_saradc: fix bitmask for channels on SARADCv2 Quentin Schulz
2024-02-23 13:40 ` Heiko Stübner
2024-02-23 12:45 ` [PATCH 2/3] iio: adc: rockchip_saradc: use mask for write_enable bitfield Quentin Schulz
2024-02-23 13:43 ` Heiko Stübner [this message]
2024-02-23 12:45 ` [PATCH 3/3] iio: adc: rockchip_saradc: replace custom logic with devm_reset_control_get_optional_exclusive Quentin Schulz
2024-02-23 13:00 ` Andy Shevchenko
2024-02-23 13:10 ` Quentin Schulz
2024-02-23 14:39 ` Andy Shevchenko
2024-02-26 20:31 ` Dragan Simic
2024-02-27 12:48 ` Andy Shevchenko
2024-02-27 14:55 ` Dragan Simic
2024-02-23 13:44 ` Heiko Stübner
2024-02-23 13:01 ` [PATCH 0/3] iio: adc: rockchip_saradc: fix bitmasking and remove custom logic for getting reset Andy Shevchenko
2024-02-24 19:25 ` Jonathan Cameron
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