From mboxrd@z Thu Jan 1 00:00:00 1970 From: marvin24@gmx.de (Marc Dietrich) Date: Sat, 27 Jul 2013 18:12:10 +0200 Subject: [PATCH 0/8] ARM: tegra: support LP1 suspend mode In-Reply-To: <1374830110-30685-1-git-send-email-josephl@nvidia.com> References: <1374830110-30685-1-git-send-email-josephl@nvidia.com> Message-ID: <2389689.JgQlW00RdN@ax5200p> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Friday 26 July 2013 17:15:02 Joseph Lo wrote: > This series adds the support of LP1 suspend mode for Tegra. > > Verified on Seaboard, Cardhu and Dalmore. tested on AC100 and worked fine, except [ 68.448007] PM: Syncing filesystems ... done. [ 71.370086] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 71.370088] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 71.371253] Suspending console(s) (use no_console_suspend to debug) [ 71.638481] PM: suspend of devices complete after 266.604 msecs [ 71.638905] PM: late suspend of devices complete after 0.417 msecs [ 71.639477] PM: noirq suspend of devices complete after 0.568 msecs [ 71.639480] Disabling non-boot CPUs ... [ 71.640242] CPU1: shutdown [ 71.641216] Entering suspend state LP1 [ 71.641267] Enabling non-boot CPUs ... [ 71.643125] CPU1: Booted secondary processor [ 71.643449] CPU1 is up [ 71.643786] PM: noirq resume of devices complete after 0.331 msecs [ 71.644300] PM: early resume of devices complete after 0.364 msecs [ 71.648038] ------------[ cut here ]------------ [ 71.648061] WARNING: CPU: 0 PID: 1025 at kernel/irq/manage.c:529 irq_set_irq_wake+0xb8/0xf0() [ 71.648064] Unbalanced IRQ 384 wake disable [ 71.648068] Modules linked in: [ 71.648075] CPU: 0 PID: 1025 Comm: bash Not tainted 3.11.0-rc2- next-20130726-00008-gef01509-dirty #6 [ 71.648107] [] (unwind_backtrace+0x0/0xf8) from [] (show_stack+0x10/0x14) [ 71.648128] [] (show_stack+0x10/0x14) from [] (dump_stack+0x80/0xc4) [ 71.648142] [] (dump_stack+0x80/0xc4) from [] (warn_slowpath_common+0x64/0x88) [ 71.648151] [] (warn_slowpath_common+0x64/0x88) from [] (warn_slowpath_fmt+0x30/0x40) [ 71.648161] [] (warn_slowpath_fmt+0x30/0x40) from [] (irq_set_irq_wake+0xb8/0xf0) [ 71.648178] [] (irq_set_irq_wake+0xb8/0xf0) from [] (tps6586x_rtc_resume+0x30/0x38) [ 71.648192] [] (tps6586x_rtc_resume+0x30/0x38) from [] (platform_pm_resume+0x2c/0x4c) [ 71.648202] [] (platform_pm_resume+0x2c/0x4c) from [] (dpm_run_callback.isra.5+0x18/0x38) [ 71.648211] [] (dpm_run_callback.isra.5+0x18/0x38) from [] (device_resume+0xb0/0x170) [ 71.648219] [] (device_resume+0xb0/0x170) from [] (dpm_resume+0xe8/0x20c) [ 71.648227] [] (dpm_resume+0xe8/0x20c) from [] (dpm_resume_end+0xc/0x18) [ 71.648245] [] (dpm_resume_end+0xc/0x18) from [] (suspend_devices_and_enter+0xdc/0x2f8) [ 71.648256] [] (suspend_devices_and_enter+0xdc/0x2f8) from [] (pm_suspend+0x174/0x1e8) [ 71.648265] [] (pm_suspend+0x174/0x1e8) from [] (state_store+0x6c/0xbc) [ 71.648285] [] (state_store+0x6c/0xbc) from [] (kobj_attr_store+0x14/0x20) [ 71.648298] [] (kobj_attr_store+0x14/0x20) from [] (sysfs_write_file+0x168/0x198) [ 71.648312] [] (sysfs_write_file+0x168/0x198) from [] (vfs_write+0xb0/0x188) [ 71.648321] [] (vfs_write+0xb0/0x188) from [] (SyS_write+0x3c/0x70) [ 71.648330] [] (SyS_write+0x3c/0x70) from [] (ret_fast_syscall+0x0/0x30) [ 71.648334] ---[ end trace e5ed8212ac4db5da ]--- [ 72.063578] mmc1: power class selection to bus width 8 failed [ 72.297753] usb 2-1: reset high-speed USB device number 2 using tegra-ehci [ 72.567736] usb 3-1: reset high-speed USB device number 2 using tegra-ehci [ 73.022058] usb 3-1.3: reset high-speed USB device number 4 using tegra- ehci [ 73.216064] usb 3-1.2: reset high-speed USB device number 3 using tegra- ehci [ 73.360225] PM: resume of devices complete after 1715.937 msecs [ 73.361008] Restarting tasks ... done. and sdcard being offline after resume (fixed by CONFIG_MMC_UNSAFE_RESUME=y). Anyway, thanks for your great work! Tested-By: Marc Dietrich > And tested with THUMB2_KERNEL as well. > > P.S. > A known issue on Dalmore, the LP1 resume may take 10 ~ 15 seconds due to > the 792MHz BCT. It can't be reproduced on Seaboard or Cardhu. And the > root cause of this is about the default settings of EMC registers that > cause the DRAM can't leave self-refresh mode immediately. If you want > to test with quick LP1 resume on Dalmore, I can provide another HACK for > this. > > Joseph Lo (8): > ARM: tegra: add common resume handling code for LP1 resuming > ARM: tegra: config the polarity of the request of sys clock > clk: tegra114: add LP1 suspend/resume support > ARM: tegra: add common LP1 suspend support > ARM: tegra30: add LP1 suspend support > ARM: tegra20: add LP1 suspend support > ARM: tegra114: add LP1 suspend support > ARM: dts: tegra: enable LP1 suspend mode > > arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- > arch/arm/boot/dts/tegra20-colibri-512.dtsi | 2 +- > arch/arm/boot/dts/tegra20-harmony.dts | 2 +- > arch/arm/boot/dts/tegra20-paz00.dts | 2 +- > arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- > arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- > arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- > arch/arm/boot/dts/tegra20-ventana.dts | 2 +- > arch/arm/boot/dts/tegra20-whistler.dts | 2 +- > arch/arm/boot/dts/tegra30-beaver.dts | 2 +- > arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- > arch/arm/mach-tegra/Makefile | 3 + > arch/arm/mach-tegra/iomap.h | 6 + > arch/arm/mach-tegra/pm-tegra20.c | 37 ++ > arch/arm/mach-tegra/pm-tegra30.c | 37 ++ > arch/arm/mach-tegra/pm.c | 121 +++++- > arch/arm/mach-tegra/pm.h | 23 ++ > arch/arm/mach-tegra/pmc.c | 36 +- > arch/arm/mach-tegra/pmc.h | 3 + > arch/arm/mach-tegra/reset-handler.S | 13 + > arch/arm/mach-tegra/reset.c | 2 + > arch/arm/mach-tegra/reset.h | 4 + > arch/arm/mach-tegra/sleep-tegra20.S | 300 ++++++++++++++ > arch/arm/mach-tegra/sleep-tegra30.S | 615 > +++++++++++++++++++++++++++++ arch/arm/mach-tegra/sleep.S | > 8 +- > arch/arm/mach-tegra/sleep.h | 18 + > drivers/clk/tegra/clk-tegra114.c | 32 ++ > 27 files changed, 1259 insertions(+), 21 deletions(-) > create mode 100644 arch/arm/mach-tegra/pm-tegra20.c > create mode 100644 arch/arm/mach-tegra/pm-tegra30.c