From: "Heiko Stübner" <heiko@sntech.de>
To: vkoul@kernel.org, kishon@kernel.org,
cristian.ciocaltea@collabora.com, andy.yan@rock-chips.com,
Algea Cao <algea.cao@rock-chips.com>
Cc: linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
Algea Cao <algea.cao@rock-chips.com>
Subject: Re: [PATCH v2] phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz error
Date: Thu, 01 May 2025 14:29:41 +0200 [thread overview]
Message-ID: <23932150.6Emhk5qWAg@diego> (raw)
In-Reply-To: <20250427095124.3354439-1-algea.cao@rock-chips.com>
Am Sonntag, 27. April 2025, 11:51:24 Mitteleuropäische Sommerzeit schrieb Algea Cao:
> When using HDMI PLL frequency division coefficient at 50.25MHz
> that is calculated by rk_hdptx_phy_clk_pll_calc(), it fails to
> get PHY LANE lock. Although the calculated values are within the
> allowable range of PHY PLL configuration.
>
> In order to fix the PHY LANE lock error and provide the expected
> 50.25MHz output, manually compute the required PHY PLL frequency
> division coefficient and add it to ropll_tmds_cfg configuration
> table.
>
> Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
next prev parent reply other threads:[~2025-05-01 12:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-27 9:51 [PATCH v2] phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz error Algea Cao
2025-05-01 12:29 ` Heiko Stübner [this message]
2025-05-14 11:31 ` Vinod Koul
2025-05-16 15:36 ` Diederik de Haas
2025-05-16 16:02 ` Cristian Ciocaltea
2025-05-16 16:28 ` Diederik de Haas
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