[PATCH 0/2] arm64: dts: rockchip: add cpu operating points and efuse node for RK3328 SoC

[PATCH 0/2] arm64: dts: rockchip: add cpu operating points and efuse node for RK3328 SoC

[Finley Xiao]

Add cpu operating points and an efuse node in the device tree for rk3228 SoC

Finley Xiao (2):
  arm64: dts: rockchip: Add cpu operating points for RK3328 SoC
  arm64: dts: rockchip: Add efuse device node for RK3328 SoC

 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 66 ++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

-- 
2.7.4

[PATCH 1/2] arm64: dts: rockchip: Add cpu operating points for RK3328 SoC

[Finley Xiao]

This patch adds basic OPP entries for RK3328 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 41 ++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 440e6bc..81fd8cb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -76,6 +76,7 @@
 			clocks = <&cru ARMCLK>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu1: cpu at 1 {
@@ -85,6 +86,7 @@
 			clocks = <&cru ARMCLK>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu2: cpu at 2 {
@@ -94,6 +96,7 @@
 			clocks = <&cru ARMCLK>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu3: cpu at 3 {
@@ -103,6 +106,7 @@
 			clocks = <&cru ARMCLK>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		l2: l2-cache0 {
@@ -110,6 +114,43 @@
 		};
 	};
 
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <950000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
+		};
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <950000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1225000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-1296000000 {
+			opp-hz = /bits/ 64 <1296000000>;
+			opp-microvolt = <1300000>;
+			clock-latency-ns = <40000>;
+		};
+	};
+
 	amba {
 		compatible = "simple-bus";
 		#address-cells = <2>;
-- 
2.7.4

[PATCH 2/2] arm64: dts: rockchip: Add efuse device node for RK3328 SoC

[Finley Xiao]

This patch adds an efuse node in the device tree for rk3228 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 81fd8cb..cc8dd80 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -367,6 +367,31 @@
 		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	efuse: efuse at ff260000 {
+		compatible = "rockchip,rk3328-efuse";
+		reg = <0x0 0xff260000 0x0 0x50>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru SCLK_EFUSE>;
+		clock-names = "pclk_efuse";
+		rockchip,efuse-size = <0x20>;
+
+		/* Data cells */
+		efuse_id: id at 7 {
+			reg = <0x07 0x10>;
+		};
+		cpu_leakage: cpu-leakage at 17 {
+			reg = <0x17 0x1>;
+		};
+		logic_leakage: logic-leakage at 19 {
+			reg = <0x19 0x1>;
+		};
+		efuse_cpu_version: cpu-version at 1a {
+			reg = <0x1a 0x1>;
+			bits = <3 3>;
+		};
+	};
+
 	saradc: adc at ff280000 {
 		compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 		reg = <0x0 0xff280000 0x0 0x100>;
-- 
2.7.4

[PATCH 1/2] arm64: dts: rockchip: Add cpu operating points for RK3328 SoC

[Heiko Stuebner]

Am Freitag, 4. August 2017, 11:33:37 CEST schrieb Finley Xiao:
> This patch adds basic OPP entries for RK3328 SoC.
> 
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

applied for 4.14


Thanks
Heiko

[PATCH 2/2] arm64: dts: rockchip: Add efuse device node for RK3328 SoC

[Heiko Stuebner]

Am Freitag, 4. August 2017, 11:33:38 CET schrieb Finley Xiao:
> This patch adds an efuse node in the device tree for rk3228 SoC.
> 
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

applied for 4.16, after the driver change landed now.


Thanks
Heiko