From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: "AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"Chen-Yu Tsai" <wenst@chromium.org>,
"Chia-I Wu" <olvaffe@gmail.com>,
"Dong Aisheng" <aisheng.dong@nxp.com>,
"Laura Nao" <laura.nao@collabora.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
"Yassine Oudjana" <y.oudjana@protonmail.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Nicolas Frattaroli" <nicolas.frattaroli@collabora.com>
Cc: kernel@collabora.com, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc
Date: Wed, 28 Jan 2026 15:55:27 +0100 [thread overview]
Message-ID: <2403222.ElGaqSPkdT@steina-w> (raw)
In-Reply-To: <5791016.31r3eYUQgx@workhorse>
Hi Nicolas,
Am Mittwoch, 28. Januar 2026, 15:11:33 CET schrieb Nicolas Frattaroli:
> On Tuesday, 27 January 2026 15:55:29 Central European Standard Time Alexander Stein wrote:
> > Hello,
> >
> > Am Freitag, 23. Januar 2026, 02:45:33 CET schrieb Stephen Boyd:
> > > Quoting Nicolas Frattaroli (2025-12-15 03:23:58)
> > > > When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock
> > > > operations, such as setting the rate or switching parents. However,
> > > > another operation that can and often does touch actual hardware state is
> > > > recalc_rate, which may also be affected by such a dependency.
> > > >
> > > > Add parent enables/disables where the recalc_rate op is called directly.
> > > >
> > > > Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
> > > > Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
> > > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > > > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> > > > Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> > > > ---
> > >
> > > Applied to clk-next
> >
> > Unfortunately this breaks my board TQMa8MPxL+MBa8MPxL on next-20260126.
> > Last lines on bootlog (earlycon is necessary)
> > > [ 1.175639] Initialise system trusted keyrings
> > > [ 1.178907] workingset: timestamp_bits=42 max_order=19 bucket_order=0
> > > [ 1.185822] NFS: Registering the id_resolver key type
> > > [ 1.190295] Key type id_resolver registered
> > > [ 1.194473] Key type id_legacy registered
> > > [ 1.198515] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
> > > [ 1.205235] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver
> > > Registering... [ 1.213235] cryptd: max_cpu_qlen set to 1000
> > > [ 1.274689] Key type asymmetric registered
> > > [ 1.275939] Asymmetric key parser 'x509' registered
> > > [ 1.280896] Block layer SCSI generic (bsg) driver version 0.4 loaded
> > > (major 242) [ 1.288278] io scheduler mq-deadline registered
> > > [ 1.292840] io scheduler kyber registered
> > > [ 1.299245] ledtrig-cpu: registered to indicate activity on CPUs
> >
> > Reverting commit 669917676e93fca5ea3c66fc9539830312bec58e fixes the problem.
>
> Hi Alexander,
>
> sorry for breaking -next.
>
> Can you try the following patch to print which clock+parent is causing
> the hang on your platform?
>
> ---
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 1b0f9d567f48..fa1443517768 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1921,13 +1921,21 @@ static unsigned long clk_recalc(struct clk_core *core,
> unsigned long rate = parent_rate;
>
> if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
> - if (core->flags & CLK_OPS_PARENT_ENABLE)
> + if (core->flags & CLK_OPS_PARENT_ENABLE) {
> + pr_info("%s: enabling parent %s for %s\n", __func__,
> + core->parent ? core->parent->name : "(null)",
> + core->name);
> clk_core_prepare_enable(core->parent);
> + }
>
> rate = core->ops->recalc_rate(core->hw, parent_rate);
>
> - if (core->flags & CLK_OPS_PARENT_ENABLE)
> + if (core->flags & CLK_OPS_PARENT_ENABLE) {
> + pr_info("%s: disabling parent %s for %s\n", __func__,
> + core->parent ? core->parent->name : "(null)",
> + core->name);
> clk_core_disable_unprepare(core->parent);
> + }
>
> clk_pm_runtime_put(core);
> }
> @@ -4038,8 +4046,12 @@ static int __clk_core_init(struct clk_core *core)
> */
> clk_core_update_duty_cycle_nolock(core);
>
> - if (core->flags & CLK_OPS_PARENT_ENABLE)
> + if (core->flags & CLK_OPS_PARENT_ENABLE) {
> + pr_info("%s: enabling parent %s for %s\n", __func__,
> + core->parent ? core->parent->name : "(null)",
> + core->name);
> clk_core_prepare_enable(core->parent);
> + }
>
> /*
> * Set clk's rate. The preferred method is to use .recalc_rate. For
> @@ -4056,8 +4068,12 @@ static int __clk_core_init(struct clk_core *core)
> rate = 0;
> core->rate = core->req_rate = rate;
>
> - if (core->flags & CLK_OPS_PARENT_ENABLE)
> + if (core->flags & CLK_OPS_PARENT_ENABLE) {
> + pr_info("%s: disabling parent %s for %s\n", __func__,
> + core->parent ? core->parent->name : "(null)",
> + core->name);
> clk_core_disable_unprepare(core->parent);
> + }
>
> /*
> * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
> ---
>
> Thanks for reporting this.
thanks for the debugging patch. I'll respond to the other thread where
Mark is active as well.
Best regards,
Alexander
> Kind regards,
> Nicolas Frattaroli
>
> >
> > Best regards,
> > Alexander
> >
>
>
>
>
>
>
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Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
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next prev parent reply other threads:[~2026-01-28 14:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 10:23 [PATCH RESEND v3 0/5] MediaTek PLL Refactors and Fixes Nicolas Frattaroli
2025-12-15 10:23 ` [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd
2026-01-27 14:55 ` Alexander Stein
2026-01-28 14:11 ` Nicolas Frattaroli
2026-01-28 14:55 ` Alexander Stein [this message]
2025-12-15 10:23 ` [PATCH RESEND v3 2/5] clk: mediatek: Refactor pll registration to pass device Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd
2025-12-15 10:24 ` [PATCH RESEND v3 3/5] clk: mediatek: Pass device to clk_hw_register for PLLs Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd
2025-12-15 10:24 ` [PATCH RESEND v3 4/5] clk: mediatek: Refactor pllfh registration to pass device Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd
2025-12-15 10:24 ` [PATCH RESEND v3 5/5] clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd
2026-01-08 12:09 ` [PATCH RESEND v3 0/5] MediaTek PLL Refactors and Fixes AngeloGioacchino Del Regno
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