From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: some question about writel implement in arm platform
Date: Thu, 16 Apr 2015 11:47:46 +0200 [thread overview]
Message-ID: <2505138.CuSGrDpcOa@wuerfel> (raw)
In-Reply-To: <CADUS3onDbAJQHnKvVavf_+nYTU1zncEu6pvSZAr=sztqgyZ6wA@mail.gmail.com>
On Thursday 16 April 2015 16:06:16 yoma sophian wrote:
>
> 2015-04-16 14:19 GMT+08:00 Arnd Bergmann <arnd@arndb.de>:
> > On Thursday 16 April 2015 13:28:41 yoma sophian wrote:
> >> hi all:
> >> the implementation of writel in ARM is writel_relaxed() with barrier
> >> before (DSB + outer cache sync).
> >>
> >> if the memory is device memory, shall we still need outer cache sync?
> >
> > Yes.
> Take my platform for example, I use Cortex A9 with PL310 L2 cache controller.
> if the memory is device memory, that mean it is un-cacheable why we
> still need to out sync off the PL310 buffer in writel operation?
The l2 sync is to ensure that prior memory writes are visible to a DMA
master that gets triggered by the writel.
If your device is not a DMA master, or the operation is unrelated to
DMA, you can use writel_relaxed().
Arnd
next prev parent reply other threads:[~2015-04-16 9:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-16 5:28 some question about writel implement in arm platform yoma sophian
2015-04-16 6:19 ` Arnd Bergmann
2015-04-16 8:06 ` yoma sophian
2015-04-16 9:47 ` Arnd Bergmann [this message]
2015-04-17 1:23 ` yoma sophian
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