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Tue, 10 Nov 2020 10:14:02 +0000 MIME-Version: 1.0 Date: Tue, 10 Nov 2020 10:14:02 +0000 From: Marc Zyngier To: James Morse Subject: Re: [PATCH 3/8] KVM: arm64: Map AArch32 cp15 register to AArch64 sysregs In-Reply-To: References: <20201102191609.265711-1-maz@kernel.org> <20201102191609.265711-4-maz@kernel.org> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <256242247e00a3dba3ab281c3a06c1dc@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: james.morse@arm.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201110_051405_815455_F4B1BF9F X-CRM114-Status: GOOD ( 24.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, Suzuki K Poulose , Julien Thierry , kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-11-03 18:29, James Morse wrote: > Hi Marc, > > On 02/11/2020 19:16, Marc Zyngier wrote: >> Move all the cp15 registers over to their AArch64 counterpart. >> This requires the annotation of a few of them (such as the usual >> DFAR/IFAR vs FAR_EL1), and a new helper that generates mask/shift >> pairs for the various configurations. > >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index 26c7c25f8a6d..137818793a4a 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -138,26 +156,16 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, >> const struct sys_reg_desc *r) >> { >> bool was_enabled = vcpu_has_cache_enabled(vcpu); >> - u64 val; >> - int reg = r->reg; >> + u64 val, mask, shift; >> >> BUG_ON(!p->is_write); >> >> - /* See the 32bit mapping in kvm_host.h */ >> - if (p->is_aarch32) >> - reg = r->reg / 2; >> + get_access_mask(r, &mask, &shift); >> >> - if (!p->is_aarch32 || !p->is_32bit) { >> - val = p->regval; >> - } else { >> - val = vcpu_read_sys_reg(vcpu, reg); >> - if (r->reg % 2) >> - val = (p->regval << 32) | (u64)lower_32_bits(val); >> - else >> - val = ((u64)upper_32_bits(val) << 32) | >> - lower_32_bits(p->regval); >> - } >> - vcpu_write_sys_reg(vcpu, val, reg); > >> + val = vcpu_read_sys_reg(vcpu, r->reg); >> + val &= ~mask; >> + val |= (p->regval & (mask >> shift)) << shift; >> + vcpu_write_sys_reg(vcpu, val, r->reg); > > I can't tell if the compiler has worked out ithat it can skip the > sys_read most of the > time... Won't some of these trap for a nested VHE hypervisor? > > | if (~mask) { > | val = vcpu_read_sys_reg(vcpu, r->reg); > | val &= ~mask; > | } Seems like a good call. I'm happy to fold that in. > > > But, as the sys_reg arrays already have indirection for this function, > why does > access_vm_reg() have to deal with this at all? Its not even needed for > all the aarch32 registers... > > > | { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), > access_aarch32_alias, NULL, MAIR_EL1 }, > > Where access_aarch32_alias() does the shift+mask and read_modify-write > on the sys_reg? I don't really like the idea of separate handlers. The whole point is to unify the two view, and I feel like having yet another indirection makes it harder to maintain. > >> kvm_toggle_cache(vcpu, was_enabled); >> return true; > >> @@ -1919,19 +1919,24 @@ static const struct sys_reg_desc >> cp14_64_regs[] = { >> */ >> static const struct sys_reg_desc cp15_regs[] = { > >> - { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR >> }, > >> + { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 >> }, > > Don't look now ... TTBRCR2 means this one is a LO/HI job. That's the problem with AArch32. You stop looking for a couple of years, and it decides to throw a new sysreg at you without any notice. WTF? > (I'm guessing that should be fixed before this series to make the > backport easy) I'll work something out as a prologue to this series. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel