From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5BD7CCD185 for ; Fri, 10 Oct 2025 15:30:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=CKUrS5jDQSXSheSIBCNgkQhgEHNgs+CbGyP1+oymFao=; b=mQJLfW4D0S3DfXCt22YfVN0eC6 3NtOU5OtbEy6m0h1Q96V9ra/1eOEfGJzrqX5gspxKwbjGonGP8s7nk9W7jgjSdI7u6Qggs07WFDaJ nD21mvwKMwfrYtcnwdQmmE0CB3btqaz9iLkIh+60ynzeGZoUS13rarEY7ggqkPd0/0AoQPKDLFuIv eWPCsJ1fDPjqVWO9qjqPH0Z/1xrkqUsF6gdTXD0gPMu/D+Hf8a/YEbwkWkhXz9GnNitkQG357kr+R 5o+lnA0tqFYAosX4WDJOjShu7reMIu1DTqwR1tVQy8p8MoWQy9SCcyMZH1RZuZk5o95wxwAzwW920 SqtRxF1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v7F4S-00000008pDq-2mXG; Fri, 10 Oct 2025 15:30:16 +0000 Received: from out-177.mta1.migadu.com ([2001:41d0:203:375::b1]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v7F4P-00000008p84-3n5q for linux-arm-kernel@lists.infradead.org; Fri, 10 Oct 2025 15:30:15 +0000 Message-ID: <25cf9d85-0f42-46d9-a4b6-618b406256f1@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1760110177; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CKUrS5jDQSXSheSIBCNgkQhgEHNgs+CbGyP1+oymFao=; b=uReHgcMIl9041kVUV2NYDBnZ17LLwXhi8mvrSAKSipFDx+9sk8nnrtoxVG+nhoQME8efbV VfpjoyvLoDgbLz2tKB9fE8dfI8ksz5xi4VLtD6mPs2LwpjGLG2Kjw7S4f0hFqCdzvhPKBf bEl3VZgTHMhk8gEeVvNpO5c5riztYKE= Date: Fri, 10 Oct 2025 23:29:15 +0800 MIME-Version: 1.0 Subject: Re: [PATCH 2/2] KVM: arm64: selftests: Cover ID_AA64ISAR3_EL1 in set_id_regs To: Mark Brown Cc: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Paolo Bonzini , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250920-kvm-arm64-id-aa64isar3-el1-v1-0-1764c1c1c96d@kernel.org> <20250920-kvm-arm64-id-aa64isar3-el1-v1-2-1764c1c1c96d@kernel.org> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Zenghui Yu In-Reply-To: <20250920-kvm-arm64-id-aa64isar3-el1-v1-2-1764c1c1c96d@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251010_083014_090709_73D3B2D5 X-CRM114-Status: GOOD ( 13.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2025/9/21 03:52, Mark Brown wrote: > We have a couple of writable bitfields in ID_AA64ISAR3_EL1 but the > set_id_regs selftest does not cover this register at all, add coverage. > > Signed-off-by: Mark Brown > --- > tools/testing/selftests/kvm/arm64/set_id_regs.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testing/selftests/kvm/arm64/set_id_regs.c > index bfb70926272d..c7c38b1a1f10 100644 > --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c > +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c > @@ -125,6 +125,13 @@ static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = { > REG_FTR_END, > }; > > +static const struct reg_ftr_bits ftr_id_aa64isar3_el1[] = { > + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FPRCVT, 0), > + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, LSFE, 0), > + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FAMINMAX, 0), > + REG_FTR_END, > +}; > + > static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = { > REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0), > REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0), > @@ -221,6 +228,7 @@ static struct test_feature_reg test_regs[] = { > TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1), > TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1), > TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1), > + TEST_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3_el1), > TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1), > TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1), > TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1), > @@ -239,6 +247,7 @@ static void guest_code(void) > GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1); > GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1); > GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1); > + GUEST_REG_SYNC(SYS_ID_AA64ISAR3_EL1); > GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1); > GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1); > GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1); Not related to this patch but seems that we forgot to sync several registers (ID_AA64PFR1, MPIDR, CLIDR) in guest to make sure the guest had seen the written value. Zenghui