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X-IronPort-AV: E=Sophos;i="5.97,229,1669071600"; d="scan'208";a="28538909" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 19 Jan 2023 16:27:41 +0100 Received: from steina-w.localnet (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 4F701280056; Thu, 19 Jan 2023 16:27:41 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Olof Johansson , Shawn Guo , Li Yang , Russell King , Marek Vasut , Marcel Ziswiler , Arnd Bergmann Cc: soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 9/9] [DNI] ARM: multi_v7_defconfig: Enable CONFIG_ARM_LPAE for multi_v7_config Date: Thu, 19 Jan 2023 16:27:39 +0100 Message-ID: <2617470.BddDVKsqQX@steina-w> Organization: TQ-Systems GmbH In-Reply-To: References: <20230119144236.3541751-1-alexander.stein@ew.tq-group.com> <20230119144236.3541751-10-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230119_072744_356637_76793380 X-CRM114-Status: GOOD ( 24.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Arnd, thanks for the fast response. Am Donnerstag, 19. Januar 2023, 16:09:05 CET schrieb Arnd Bergmann: > On Thu, Jan 19, 2023, at 15:42, Alexander Stein wrote: > > This is necessary to support PCIe on LS1021A. > > > > Signed-off-by: Alexander Stein > > Can you explain why this is actually required? I can see that the > ranges in the PCIe device point to a high address (0x4000000000, > 2^40), but I can't tell if this is hardwired in the SoC or a > setting that is applied by software (either the bootloader or > the PCIe driver). The RM ([1]) memory map (Table 2-1) says that 'PCI Express 1' is located at '400000_0000', 'PCI Express 2' at '480000_0000', so I assume this is hardcoded in SoC. It also explicitly lists in that table PCIe 1&2 is only accessible with 40-bit addressing. > If you can reprogram the memory map, I would expect this to fit > easily into the 32-bit address space, with 1GB for DDR3 memory > and 1GB for PCIe BARs. I'm not sure which part of memory map you can reprogram and where, but I guess this is fixed on this SoC. > I don't mind having a defconfig with LPAE enabled, I think this > can be done using a Makefile target that applies a config > fragment on top of the normal multi_v7_defconfig, you can find > some examples in arch/powerpc/configs/*.config. Ah, nice. This can be a good starter. Thanks. Best regards, Alexander [1] https://www.nxp.com/webapp/Download?colCode=LS1021ARM _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel