Re: [PATCH] arm64: kernel: Disable CNP on HiSilicon HIP09

[Zeng Heng <zengheng@huaweicloud.com>]

Hi Vladimir,

On 2026/5/26 20:10, Vladimir Murzin wrote:
> Hi,
> 
> On 5/26/26 02:57, Zeng Heng wrote:
>> From: Tong Tiangen <tongtiangen@huawei.com>
>>
>> HiSilicon HIP09 implements TLB entry matching behavior that deviates
>> from the ARM architecture specification when the CNP (Common not Private)
>> bit is set in TTBRx_ELx.
>>
>> When TTBRx.CNP=1, TLB entries may be incorrectly shared between CPU
>> cores, leading to TLB conflicts and stale mappings. This affects
>> coherency and can result in incorrect translations.
>>
>> Add the hardware erratum workaround (Hisilicon erratum 162100125) to
>> disable CNP on affected HIP09 cores.
>>
>> Signed-off-by: Tong Tiangen <tongtiangen@huawei.com>
>> Signed-off-by: Zeng Heng <zengheng4@huawei.com>
>> ---
>>   Documentation/arch/arm64/silicon-errata.rst |  2 ++
>>   arch/arm64/Kconfig                          | 15 +++++++++++++++
>>   arch/arm64/kernel/cpu_errata.c              |  7 +++++++
>>   arch/arm64/kernel/cpufeature.c              |  3 ++-
>>   arch/arm64/tools/cpucaps                    |  1 +
>>   5 files changed, 27 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
>> index 211119ce7adc..cd50059edb85 100644
>> --- a/Documentation/arch/arm64/silicon-errata.rst
>> +++ b/Documentation/arch/arm64/silicon-errata.rst
>> @@ -284,6 +284,8 @@ stable kernels.
>>   +----------------+-----------------+-----------------+-----------------------------+
>>   | Hisilicon      | Hip09           | #162100801      | HISILICON_ERRATUM_162100801 |
>>   +----------------+-----------------+-----------------+-----------------------------+
>> +| Hisilicon      | Hip09           | #162100125      | HISILICON_ERRATUM_162100125 |
>> ++----------------+-----------------+-----------------+-----------------------------+
>>   +----------------+-----------------+-----------------+-----------------------------+
>>   | Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |
>>   +----------------+-----------------+-----------------+-----------------------------+
>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>> index fe60738e5943..ed6207c75b54 100644
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/Kconfig
>> @@ -1273,6 +1273,21 @@ config HISILICON_ERRATUM_162100801
>>   
>>   	  If unsure, say Y.
>>   
>> +config HISILICON_ERRATUM_162100125
>> +	bool "Hisilicon erratum 162100125"
>> +	default y
>> +	help
>> +	  On HiSilicon HIP09, TLB entry matching behavior when CNP
>> +	  (TTBRx.CNP=1) is enabled differs from the ARM architecture
>> +	  specification.
>> +
>> +	  TLB entries may be incorrectly shared between CPUs, potentially
>> +	  causing TLB conflicts and stale mappings.
>> +
>> +	  Disable CNP support for affected HiSilicon HIP09 cores.
>> +
>> +	  If unsure, say Y.
>> +
>>   config QCOM_FALKOR_ERRATUM_1003
>>   	bool "Falkor E1003: Incorrect translation due to ASID change"
>>   	default y
>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
>> index 5377e4c2eba2..26d9677a20fc 100644
>> --- a/arch/arm64/kernel/cpu_errata.c
>> +++ b/arch/arm64/kernel/cpu_errata.c
>> @@ -968,6 +968,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
>>   		.matches = has_impdef_pmuv3,
>>   		.cpu_enable = cpu_enable_impdef_pmuv3_traps,
>>   	},
>> +#ifdef CONFIG_HISILICON_ERRATUM_162100125
>> +	{
>> +		.desc = "Hisilicon erratum 162100125",
>> +		.capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100125,
>> +		ERRATA_MIDR_ALL_VERSIONS(MIDR_HISI_HIP09),
>> +	},
>> +#endif
>>   	{
>>   	}
>>   };
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index 6d53bb15cf7b..c4b0db77a58a 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -1785,7 +1785,8 @@ has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
>>   	if (is_kdump_kernel())
>>   		return false;
>>   
>> -	if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
>> +	if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP) ||
>> +	    cpus_have_cap(ARM64_WORKAROUND_HISILICON_ERRATUM_162100125))
>>   		return false;
> 
> Since we now have a second user for this workaround, would it
> make sense to:
> 1. factor out the existing ARM64_WORKAROUND_NVIDIA_CARMEL_CNP into a common capability,
>     for example ARM64_WORKAROUND_DISABLE_CNP
> 2. wire up erratum 162100125 to use the common ARM64_WORKAROUND_DISABLE_CNP capability?
> 
> Cheers
> Vladimir
> 

This makes sense to me. Thanks for the reminder.

Best regards,
Zeng Heng

>>   
>>   	return has_cpuid_feature(entry, scope);
>> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
>> index 811c2479e82d..b797d4893adc 100644
>> --- a/arch/arm64/tools/cpucaps
>> +++ b/arch/arm64/tools/cpucaps
>> @@ -128,3 +128,4 @@ WORKAROUND_REPEAT_TLBI
>>   WORKAROUND_SPECULATIVE_AT
>>   WORKAROUND_SPECULATIVE_SSBS
>>   WORKAROUND_SPECULATIVE_UNPRIV_LOAD
>> +WORKAROUND_HISILICON_ERRATUM_162100125
>> -- 2.43.0
>>
> 
> 
>