From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE295C4338F for ; Wed, 28 Jul 2021 09:55:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 56AAB60F9C for ; Wed, 28 Jul 2021 09:55:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 56AAB60F9C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BZSv64w7HO8RAzFQFWFobhvsmodyxtDSdMy1zP0gfjM=; b=VxWvdZiht7Hkv+ EbKR7RIaUAH4MNRVhgBtyN1YAUKP89CPPUakCFXvSNugFd3c2JhmW7Rb2RBKR0dhgVLKoTCI98N3w QHrJGyqtWdJ6QUSxC9Ck1T2BuDpUrbGpwoymegcC1/+X2lMqqlyq5RG4MK9g7L1gyzW+vMNQirae7 pF7xcVpWnfKoazhP8itEPpQ3Hh8Z8f/t6iNUMl7Svu2W5UE+3Y/etYrxbMuaxk+5hV+e4pOPQ+XdP ddNisI1eVtZ2KDy62Chno47zjLyXr7AlRVDc/H7DINBPgalCItAt/JywGpmjSy0XdDf2/IVEI7Cjv 3xUsgBvXGrKwFx1bXQig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m8gGI-000HMb-KY; Wed, 28 Jul 2021 09:54:02 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m8gGE-000HLo-Ra; Wed, 28 Jul 2021 09:54:00 +0000 Received: from [95.90.166.74] (helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1m8gGB-0004qG-7D; Wed, 28 Jul 2021 11:53:55 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Yunhao Tian , Stephen Boyd Cc: t123yh.xyz@gmail.com, Yunhao Tian , Michael Turquette , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH] clk: rk3308: make ddrphy4x clock critical Date: Wed, 28 Jul 2021 11:53:54 +0200 Message-ID: <2634451.ElGaqSPkdT@diego> In-Reply-To: <162734809017.2368309.7901135942001140161@swboyd.mtv.corp.google.com> References: <162734809017.2368309.7901135942001140161@swboyd.mtv.corp.google.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210728_025358_951994_760A603E X-CRM114-Status: GOOD ( 25.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Am Dienstag, 27. Juli 2021, 03:08:10 CEST schrieb Stephen Boyd: > Quoting Yunhao Tian (2021-07-21 05:48:16) > > Currently, no driver support for DDR memory controller (DMC) is present, > > as a result, no driver is explicitly consuming the ddrphy clock. This means > > that VPLL1 (parent of ddr clock) will be shutdown if we enable > > and then disable any child clock of VPLL1 (e.g. SCLK_I2S0_8CH_TX). > > If VPLL1 is disabled, the whole system will freeze, because the DDR > > controller will lose its clock. So, it's necessary to prevent VPLL1 from > > shutting down, by marking the ddrphy4x CLK_IS_CRITICAL. > > > > This bug was discovered when I was porting rockchip_i2s_tdm driver to > > mainline kernel from Rockchip 4.4 kernel. I guess that other Rockchip > > SoCs without DMC driver may need the same patch. If this applies to > > other devices, please let us know. > > > > Signed-off-by: Yunhao Tian > > --- > > drivers/clk/rockchip/clk-rk3308.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c > > index 2c3bd0c749f2..6be077166330 100644 > > --- a/drivers/clk/rockchip/clk-rk3308.c > > +++ b/drivers/clk/rockchip/clk-rk3308.c > > @@ -564,7 +564,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = { > > COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED, > > RK3308_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 3, DFLAGS, > > RK3308_CLKGATE_CON(0), 10, GFLAGS), > > - GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED, > > + GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, > > Is it not enabled by default? All gates are enabled by default, but this gate shares a common parent tree down to a pll, so if another leaf-user is disabling their part, this untracked clock would get disabled as well. On that note, I remember a sort of CLK_HANDOFF was planned way back in the past, meaning clock is critical until a driver picks it up, after this the driver is responsible for it. Did that get any momentum? Heiko _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel