[PATCH 1/4] arm64: dts: rk3399: add missing qos node

[PATCH 1/4] arm64: dts: rk3399: add missing qos node

[Kever Yang]

Add qos setting reg for some peripheral like sd, usb, pcie.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 45 ++++++++++++++++++++++++++++----
 1 file changed, 40 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index f4f3c96..387ae34 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -769,11 +769,6 @@
 		status = "disabled";
 	};
 
-	qos_sd: qos at ffa74000 {
-		compatible = "syscon";
-		reg = <0x0 0xffa74000 0x0 0x20>;
-	};
-
 	qos_emmc: qos at ffa58000 {
 		compatible = "syscon";
 		reg = <0x0 0xffa58000 0x0 0x20>;
@@ -784,6 +779,41 @@
 		reg = <0x0 0xffa5c000 0x0 0x20>;
 	};
 
+	qos_pcie: qos at ffa60080 {
+		compatible = "syscon";
+		reg = <0x0 0xffa60080 0x0 0x20>;
+	};
+
+	qos_usb_host0: qos at ffa60100 {
+		compatible = "syscon";
+		reg = <0x0 0xffa60100 0x0 0x20>;
+	};
+
+	qos_usb_host1: qos at ffa60180 {
+		compatible = "syscon";
+		reg = <0x0 0xffa60180 0x0 0x20>;
+	};
+
+	qos_usb_otg0: qos at ffa70000 {
+		compatible = "syscon";
+		reg = <0x0 0xffa70000 0x0 0x20>;
+	};
+
+	qos_usb_otg1: qos at ffa70080 {
+		compatible = "syscon";
+		reg = <0x0 0xffa70080 0x0 0x20>;
+	};
+
+	qos_sd: qos at ffa74000 {
+		compatible = "syscon";
+		reg = <0x0 0xffa74000 0x0 0x20>;
+	};
+
+	qos_sdioaudio: qos at ffa76000 {
+		compatible = "syscon";
+		reg = <0x0 0xffa76000 0x0 0x20>;
+	};
+
 	qos_hdcp: qos at ffa90000 {
 		compatible = "syscon";
 		reg = <0x0 0xffa90000 0x0 0x20>;
@@ -854,6 +884,11 @@
 		reg = <0x0 0xffad0000 0x0 0x20>;
 	};
 
+	qos_perihp: qos at ffad8080 {
+		compatible = "syscon";
+		reg = <0x0 0xffad8080 0x0 0x20>;
+	};
+
 	qos_gpu: qos at ffae0000 {
 		compatible = "syscon";
 		reg = <0x0 0xffae0000 0x0 0x20>;
-- 
1.9.1

[PATCH 2/4] arm64: dts: rk3399: add power domain for some peripheral

[Kever Yang]

Add power domain for sd, usb, edp.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 36 +++++++++++++++++++++++++++-----
 1 file changed, 31 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 387ae34..9d44c19 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -947,6 +947,10 @@
 			};
 
 			/* These power domains are grouped by VD_LOGIC */
+			pd_edp at RK3399_PD_EDP {
+				reg = <RK3399_PD_EDP>;
+				clocks = <&cru PCLK_EDP_CTRL>;
+			};
 			pd_emmc at RK3399_PD_EMMC {
 				reg = <RK3399_PD_EMMC>;
 				clocks = <&cru ACLK_EMMC>;
@@ -958,11 +962,33 @@
 					 <&cru PCLK_GMAC>;
 				pm_qos = <&qos_gmac>;
 			};
-			pd_sd at RK3399_PD_SD {
-				reg = <RK3399_PD_SD>;
-				clocks = <&cru HCLK_SDMMC>,
-					 <&cru SCLK_SDMMC>;
-				pm_qos = <&qos_sd>;
+			pd_perihp at RK3399_PD_PERIHP {
+				reg = <RK3399_PD_PERIHP>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&cru ACLK_PERIHP>;
+				pm_qos = <&qos_perihp>,
+					 <&qos_pcie>,
+					 <&qos_usb_host0>,
+					 <&qos_usb_host1>;
+
+				pd_sd at RK3399_PD_SD {
+					reg = <RK3399_PD_SD>;
+					clocks = <&cru HCLK_SDMMC>,
+						 <&cru SCLK_SDMMC>;
+					pm_qos = <&qos_sd>;
+				};
+			};
+			pd_sdioaudio at RK3399_PD_SDIOAUDIO {
+				reg = <RK3399_PD_SDIOAUDIO>;
+				clocks = <&cru HCLK_SDIO>;
+				pm_qos = <&qos_sdioaudio>;
+			};
+			pd_usb3 at RK3399_PD_USB3 {
+				reg = <RK3399_PD_USB3>;
+				clocks = <&cru ACLK_USB3>;
+				pm_qos = <&qos_usb_otg0>,
+					 <&qos_usb_otg1>;
 			};
 			pd_vio at RK3399_PD_VIO {
 				reg = <RK3399_PD_VIO>;
-- 
1.9.1

[PATCH 2/4] arm64: dts: rk3399: add power domain for some peripheral

[Heiko Stuebner]

Am Mittwoch, 12. April 2017, 15:10:42 CEST schrieb Kever Yang:
> Add power domain for sd, usb, edp.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

applied for 4.13


Thanks
Heiko

[PATCH 2/4] arm64: dts: rk3399: add power domain for some peripheral

[Heiko Stübner]

Am Dienstag, 9. Mai 2017, 23:40:29 CEST schrieb Heiko Stuebner:
> Am Mittwoch, 12. April 2017, 15:10:42 CEST schrieb Kever Yang:
> > Add power domain for sd, usb, edp.
> > 
> > Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> 
> applied for 4.13

and dropped again.

Actual testing revealed that I now get "synchronous external aborts" with
this patch applied.

The power-domain driver now probably disables some domain that should've 
stayed on and I guess the only thing missing is probably some power-domains
reference in some device node in rk3399.dtsi.

It would be cool, if you could investigate which one it is :-) .


Heiko

[PATCH 4/4] arm64: dts: rk3399: add pinctrl for some peripheral

[Kever Yang]

Add pinctrl for sdio, sdmmc, pcie, spdif, hdmi.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 113 +++++++++++++++++++++++++++++++
 1 file changed, 113 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 54a5340..0096c70 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1737,6 +1737,91 @@
 			};
 		};
 
+		sdio0 {
+			sdio0_bus1: sdio0-bus1 {
+				rockchip,pins =
+					<2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio0_bus4: sdio0-bus4 {
+				rockchip,pins =
+					<2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
+					<2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
+					<2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
+					<2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio0_cmd: sdio0-cmd {
+				rockchip,pins =
+					<2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio0_clk: sdio0-clk {
+				rockchip,pins =
+					<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			sdio0_cd: sdio0-cd {
+				rockchip,pins =
+					<2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio0_pwr: sdio0-pwr {
+				rockchip,pins =
+					<2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio0_bkpwr: sdio0-bkpwr {
+				rockchip,pins =
+					<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio0_wp: sdio0-wp {
+				rockchip,pins =
+					<0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio0_int: sdio0-int {
+				rockchip,pins =
+					<0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
+			};
+		};
+
+		sdmmc {
+			sdmmc_bus1: sdmmc-bus1 {
+				rockchip,pins =
+					<4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdmmc_bus4: sdmmc-bus4 {
+				rockchip,pins =
+					<4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
+					<4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
+					<4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
+					<4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdmmc_clk: sdmmc-clk {
+				rockchip,pins =
+					<4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			sdmmc_cmd: sdmmc-cmd {
+				rockchip,pins =
+					<4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdmmc_cd: sdmcc-cd {
+				rockchip,pins =
+					<0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdmmc_wp: sdmmc-wp {
+				rockchip,pins =
+					<0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+			};
+		};
+
 		sleep {
 			ap_pwroff: ap-pwroff {
 				rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
@@ -1752,6 +1837,11 @@
 				rockchip,pins =
 					<4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
 			};
+
+			spdif_bus_1: spdif-bus-1 {
+				rockchip,pins =
+					<3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
+			};
 		};
 
 		spi0 {
@@ -2011,6 +2101,19 @@
 			};
 		};
 
+		hdmi {
+			hdmi_i2c_xfer: hdmi-i2c-xfer {
+				rockchip,pins =
+					<4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
+					<4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
+			};
+
+			hdmi_cec: hdmi-cec {
+				rockchip,pins =
+					<4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
 		pcie {
 			pcie_clkreqn: pci-clkreqn {
 				rockchip,pins =
@@ -2021,6 +2124,16 @@
 				rockchip,pins =
 					<4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
 			};
+
+			pcie_clkreqn_cpm: pci-clkreqn-cpm {
+				rockchip,pins =
+					<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+			pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
+				rockchip,pins =
+					<4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
 		};
 
 	};
-- 
1.9.1

[PATCH 4/4] arm64: dts: rk3399: add pinctrl for some peripheral

[Heiko Stuebner]

Am Mittwoch, 12. April 2017, 15:10:44 CEST schrieb Kever Yang:
> Add pinctrl for sdio, sdmmc, pcie, spdif, hdmi.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

applied for 4.13, after adapting for the not applied patch 3/4.


Thanks
Heiko

[PATCH 1/4] arm64: dts: rk3399: add missing qos node

[Heiko Stuebner]

Am Mittwoch, 12. April 2017, 15:10:41 CEST schrieb Kever Yang:
> Add qos setting reg for some peripheral like sd, usb, pcie.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

applied for 4.13


Thanks
Heiko

[PATCH 3/4] ARM: dts: rockchip: use pin constants to describe IO in pinctrl

[Heiko Stuebner]

Am Mittwoch, 12. April 2017, 15:10:43 CEST schrieb Kever Yang:
> Use command below to replace the IO naming in pinctrl:
> sed -i -e 's/ 31 RK_FUNC_/ RK_PD7 RK_FUNC_/' arch/arm/boot/dts/rk*
> sed -i -e 's/ 0 RK_FUNC_/ RK_PA0 RK_FUNC_/'
> arch/arm64/boot/dts/rockchip/*
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

I'm not sure, if we really want to mass-convert each and every pin.
All pins in use right now seem to be working and it hides other
history/blame for these entries.

In any case though, this needs to be split into separate arm32/arm64
patches.


Heiko

[PATCH 3/4] ARM: dts: rockchip: use pin constants to describe IO in pinctrl

[Kever Yang]

Heiko,


On 05/10/2017 05:43 AM, Heiko Stuebner wrote:
> Am Mittwoch, 12. April 2017, 15:10:43 CEST schrieb Kever Yang:
>> Use command below to replace the IO naming in pinctrl:
>> sed -i -e 's/ 31 RK_FUNC_/ RK_PD7 RK_FUNC_/' arch/arm/boot/dts/rk*
>> sed -i -e 's/ 0 RK_FUNC_/ RK_PA0 RK_FUNC_/'
>> arch/arm64/boot/dts/rockchip/*
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> I'm not sure, if we really want to mass-convert each and every pin.
> All pins in use right now seem to be working and it hides other
> history/blame for these entries.

Do you mean you want to leave the code already there as is, and new
code using MACRO define for IO?

This sounds reasonable, I can agree on this. I send this patch because I 
see there is
a patch from Andy using MACRO for many IOs, but not complete enough
and my patch suppose to make all Rockchip IO has update.

Thanks,
- Kever
>
> In any case though, this needs to be split into separate arm32/arm64
> patches.
>
>
> Heiko
>

[PATCH 3/4] ARM: dts: rockchip: use pin constants to describe IO in pinctrl

[Heiko Stuebner]

Hi Kever,

Am Mittwoch, 10. Mai 2017, 09:25:25 CEST schrieb Kever Yang:
> On 05/10/2017 05:43 AM, Heiko Stuebner wrote:
> > Am Mittwoch, 12. April 2017, 15:10:43 CEST schrieb Kever Yang:
> >> Use command below to replace the IO naming in pinctrl:
> >> sed -i -e 's/ 31 RK_FUNC_/ RK_PD7 RK_FUNC_/' arch/arm/boot/dts/rk*
> >> sed -i -e 's/ 0 RK_FUNC_/ RK_PA0 RK_FUNC_/'
> >> arch/arm64/boot/dts/rockchip/*
> >>
> >> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> > I'm not sure, if we really want to mass-convert each and every pin.
> > All pins in use right now seem to be working and it hides other
> > history/blame for these entries.
> 
> Do you mean you want to leave the code already there as is, and new
> code using MACRO define for IO?
> 
> This sounds reasonable, I can agree on this. I send this patch because I 
> see there is
> a patch from Andy using MACRO for many IOs, but not complete enough
> and my patch suppose to make all Rockchip IO has update.

As I said, I'm really not sure. On the one hand it's nicer and it will
be easier to check devicetree against schematics, but mass-converting
them makes me anxious. Andy did convert the rk3288-popmetal
board which is somewhat sparsely used I think. If anything breaks with
Firefly, Rock, Veyron etc we might make a lot of people unhappy :-) .

But having boards use both paradigms at the same time (pin number and
names) could also be confusing.

> > In any case though, this needs to be split into separate arm32/arm64
> > patches.

Maybe we could split not only on the arm/arm64 border, but also on
something like soc-level (rk3188, rk3288, rk3368). That way the amount
of changes per patch would go down making review easier :-) .


Just to make sure you saw it, I've also had to drop patch2 again (see
separate response from yesterday).


Heiko