From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32499CA0ED1 for ; Mon, 18 Aug 2025 13:42:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=EMQjlP0jqiiTFCiCqjpa9LEtzKzmxzTI2QJgAqC9ZnU=; b=exCkmzHdltI6MWUUeA439y5BfW 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Content-Transfer-Encoding:cc:content-transfer-encoding: content-type:date:from:message-id:mime-version:reply-to:subject: to; b=aFhq5C3SL0ZgB9EIlXQ5qWuMOG6Qchh6kcOWxOGESf1ICk6JZXAkXCSup8METNNi UF/9WoGaSmZ920dKElR2yghPlAZTlVkrytZNiaQJJjvpjvuPv0j5ZSfZERmBXwi9j 41D/n0Wsytqa418D4rfzgRrGl17lCeOaWnVzakI5ZxOjhnIs+d8uZln7iuJBpvEMo C3WS2FmieDjzzFp6r+EHqiFxgbwUEBUnKWdOZC5kKSTBj8nosstPH6sIdmHvh2uPv dMVWgGDEclWBA4AQ0I7RV0L7K4w8Kbkirk9G/CkbPfCtjnUOnBVwJW590ul61Fw9S Wj5kDClVCTVv/m5rKQ== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from [192.168.1.105] ([79.235.128.112]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MNbkp-1vBQXX3pJD-00U5ea; Mon, 18 Aug 2025 12:51:49 +0200 Message-ID: <26680a60-e9f1-4c71-acc9-8c0fb8f6b032@gmx.net> Date: Mon, 18 Aug 2025 12:51:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparing To: =?UTF-8?Q?Ma=C3=ADra_Canal?= , Michael Turquette , Stephen Boyd , Nicolas Saenz Julienne , Florian Fainelli , Maxime Ripard , Melissa Wen , Iago Toral Quiroga , Dom Cobley , Dave Stevenson , Philipp Zabel Cc: linux-clk@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Broadcom internal kernel review list , kernel-dev@igalia.com References: <20250731-v3d-power-management-v2-0-032d56b01964@igalia.com> <20250731-v3d-power-management-v2-2-032d56b01964@igalia.com> Content-Language: en-US From: Stefan Wahren Autocrypt: addr=wahrenst@gmx.net; keydata= xjMEZ1dOJBYJKwYBBAHaRw8BAQdA7H2MMG3q8FV7kAPko5vOAeaa4UA1I0hMgga1j5iYTTvN IFN0ZWZhbiBXYWhyZW4gPHdhaHJlbnN0QGdteC5uZXQ+wo8EExYIADcWIQT3FXg+ApsOhPDN NNFuwvLLwiAwigUCZ1dOJAUJB4TOAAIbAwQLCQgHBRUICQoLBRYCAwEAAAoJEG7C8svCIDCK JQ4BAP4Y9uuHAxbAhHSQf6UZ+hl5BDznsZVBJvH8cZe2dSZ6AQCNgoc1Lxw1tvPscuC1Jd1C TZomrGfQI47OiiJ3vGktBc44BGdXTiQSCisGAQQBl1UBBQEBB0B5M0B2E2XxySUQhU6emMYx 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List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Ma=C3=ADra, Am 31.07.25 um 23:06 schrieb Ma=C3=ADra Canal: > Currently, when we prepare or unprepare RPi's clocks, we don't actually > enable/disable the firmware clock. This means that > `clk_disable_unprepare()` doesn't actually change the clock state at > all, nor does it lowers the clock rate. > > From the Mailbox Property Interface documentation [1], we can see that > we should use `RPI_FIRMWARE_SET_CLOCK_STATE` to set the clock state > off/on. Therefore, use `RPI_FIRMWARE_SET_CLOCK_STATE` to create a > prepare and an unprepare hook for RPi's firmware clock. > > As now the clocks are actually turned off, some of them are now marked > CLK_IS_CRITICAL, as those are required to be on during the whole system > operation. > > Link: https://github.com/raspberrypi/firmware/wiki/Mailbox-property-inte= rface [1] > Signed-off-by: Ma=C3=ADra Canal sorry this late reply, but I was in the holidays. In general the approach looks good to me. Very old vc4 firmware versions= =20 doesn't support RPI_FIRMWARE_SET_CLOCK_STATE. I mention this because=20 sometimes the setups on kernelci.org are not always up to date. But I=20 think we should be save in this case. Reviewed-by: Stefan Wahren > > --- > > About the pixel clock: currently, if we actually disable the pixel > clock during a hotplug, the system will crash. This happens in the > RPi 4. > > The crash happens after we disabled the CRTC (thus, the pixel clock), > but before the end of atomic commit tail. As vc4's pixel valve doesn't > directly hold a reference to its clock =E2=80=93 we use the HDMI encoder= to > manage the pixel clock =E2=80=93 I believe we might be disabling the clo= ck > before we should. > > After this investigation, I decided to keep things as they current are: > the pixel clock is never disabled, as fixing it would go out of > the scope of this series. > --- > drivers/clk/bcm/clk-raspberrypi.c | 56 +++++++++++++++++++++++++++++++= +++++++- > 1 file changed, 55 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-ras= pberrypi.c > index 166d0bec380310e8b98f91568efa4aa88401af4f..70acfa68827d84670c645bed= d17bf0e181aadfbb 100644 > --- a/drivers/clk/bcm/clk-raspberrypi.c > +++ b/drivers/clk/bcm/clk-raspberrypi.c > @@ -68,6 +68,7 @@ struct raspberrypi_clk_variant { > char *clkdev; > unsigned long min_rate; > bool minimize; > + u32 flags; > }; > =20 > static struct raspberrypi_clk_variant > @@ -75,6 +76,7 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] =3D = { > [RPI_FIRMWARE_ARM_CLK_ID] =3D { > .export =3D true, > .clkdev =3D "cpu0", > + .flags =3D CLK_IS_CRITICAL, > }, > [RPI_FIRMWARE_CORE_CLK_ID] =3D { > .export =3D true, > @@ -90,6 +92,12 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] =3D= { > * always use the minimum the drivers will let us. > */ > .minimize =3D true, > + > + /* > + * It should never be disabled as it drives the bus for > + * everything else. > + */ > + .flags =3D CLK_IS_CRITICAL, > }, > [RPI_FIRMWARE_M2MC_CLK_ID] =3D { > .export =3D true, > @@ -115,6 +123,15 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = =3D { > * drivers will let us. > */ > .minimize =3D true, > + > + /* > + * As mentioned above, this clock is disabled during boot, > + * the firmware will skip the HSM initialization, resulting > + * in a bus lockup. Therefore, make sure it's enabled > + * during boot, but after it, it can be enabled/disabled > + * by the driver. > + */ > + .flags =3D CLK_IGNORE_UNUSED, > }, > [RPI_FIRMWARE_V3D_CLK_ID] =3D { > .export =3D true, > @@ -123,10 +140,12 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = =3D { > [RPI_FIRMWARE_PIXEL_CLK_ID] =3D { > .export =3D true, > .minimize =3D true, > + .flags =3D CLK_IS_CRITICAL, > }, > [RPI_FIRMWARE_HEVC_CLK_ID] =3D { > .export =3D true, > .minimize =3D true, > + .flags =3D CLK_IS_CRITICAL, > }, > [RPI_FIRMWARE_ISP_CLK_ID] =3D { > .export =3D true, > @@ -135,6 +154,7 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = =3D { > [RPI_FIRMWARE_PIXEL_BVB_CLK_ID] =3D { > .export =3D true, > .minimize =3D true, > + .flags =3D CLK_IS_CRITICAL, > }, > [RPI_FIRMWARE_VEC_CLK_ID] =3D { > .export =3D true, > @@ -265,7 +285,41 @@ static int raspberrypi_fw_dumb_determine_rate(struc= t clk_hw *hw, > return 0; > } > =20 > +static int raspberrypi_fw_prepare(struct clk_hw *hw) > +{ > + const struct raspberrypi_clk_data *data =3D clk_hw_to_data(hw); > + struct raspberrypi_clk *rpi =3D data->rpi; > + u32 state =3D RPI_FIRMWARE_STATE_ENABLE_BIT; > + int ret; > + > + ret =3D raspberrypi_clock_property(rpi->firmware, data, > + RPI_FIRMWARE_SET_CLOCK_STATE, &state); > + if (ret) > + dev_err_ratelimited(rpi->dev, > + "Failed to set clock %s state to on: %d\n", > + clk_hw_get_name(hw), ret); > + > + return ret; > +} > + > +static void raspberrypi_fw_unprepare(struct clk_hw *hw) > +{ > + const struct raspberrypi_clk_data *data =3D clk_hw_to_data(hw); > + struct raspberrypi_clk *rpi =3D data->rpi; > + u32 state =3D 0; > + int ret; > + > + ret =3D raspberrypi_clock_property(rpi->firmware, data, > + RPI_FIRMWARE_SET_CLOCK_STATE, &state); > + if (ret) > + dev_err_ratelimited(rpi->dev, > + "Failed to set clock %s state to off: %d\n", > + clk_hw_get_name(hw), ret); > +} > + > static const struct clk_ops raspberrypi_firmware_clk_ops =3D { > + .prepare =3D raspberrypi_fw_prepare, > + .unprepare =3D raspberrypi_fw_unprepare, > .is_prepared =3D raspberrypi_fw_is_prepared, > .recalc_rate =3D raspberrypi_fw_get_rate, > .determine_rate =3D raspberrypi_fw_dumb_determine_rate, > @@ -295,7 +349,7 @@ static struct clk_hw *raspberrypi_clk_register(struc= t raspberrypi_clk *rpi, > if (!init.name) > return ERR_PTR(-ENOMEM); > init.ops =3D &raspberrypi_firmware_clk_ops; > - init.flags =3D CLK_GET_RATE_NOCACHE; > + init.flags =3D variant->flags | CLK_GET_RATE_NOCACHE; > =20 > data->hw.init =3D &init; > =20 >