[PATCH 0/6] ARM: rockchip: add initial support for rk3288

[PATCH 0/6] ARM: rockchip: add initial support for rk3288

[Heiko Stübner]

This series adds the initial support for Rockchip rk3288 socs including
debug uart and devicetree files for the rk3288 evaluation board and
enables these boards to boot into an initramfs.

The series depends on an updated bootloader, which must start the timer
supplying the architected timer, which we will hopefully get in the next
days. It also depends on the patch
    "irqchip: gic: Add binding probe for ARM GIC400"
which will hopefully make it into the irqchip tree shortly.


Heiko Stuebner (6):
  dt-bindings: arm: add arm,cortex-a12 cpu compatible property
  ARM: rockchip: add debug uart used by rk3288
  ARM: Kconfig: set default gpio number for rockchip SoCs
  ARM: rockchip: enable support for RK3288 SoCs
  ARM: dts: rockchip: add core rk3288 dtsi
  ARM: dts: add rk3288 evaluation board

 Documentation/devicetree/bindings/arm/cpus.txt |   1 +
 arch/arm/Kconfig                               |   1 +
 arch/arm/Kconfig.debug                         |  12 +-
 arch/arm/boot/dts/rk3288-evb-act8846.dts       | 136 ++++++
 arch/arm/boot/dts/rk3288-evb-rk808.dts         |  19 +
 arch/arm/boot/dts/rk3288-evb.dtsi              |  77 ++++
 arch/arm/boot/dts/rk3288.dtsi                  | 561 +++++++++++++++++++++++++
 arch/arm/mach-rockchip/Kconfig                 |   1 +
 arch/arm/mach-rockchip/rockchip.c              |   1 +
 9 files changed, 808 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/rk3288-evb-act8846.dts
 create mode 100644 arch/arm/boot/dts/rk3288-evb-rk808.dts
 create mode 100644 arch/arm/boot/dts/rk3288-evb.dtsi
 create mode 100644 arch/arm/boot/dts/rk3288.dtsi

-- 
1.9.0

[PATCH 1/6] dt-bindings: arm: add arm, cortex-a12 cpu compatible property

[Heiko Stübner]

This is necessary for the new RK3288 soc.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 1fe72a0..620a1a8 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -152,6 +152,7 @@ nodes to be present and contain the properties described below.
 			    "arm,cortex-a7"
 			    "arm,cortex-a8"
 			    "arm,cortex-a9"
+			    "arm,cortex-a12"
 			    "arm,cortex-a15"
 			    "arm,cortex-a53"
 			    "arm,cortex-a57"
-- 
1.9.0

[PATCH 2/6] ARM: rockchip: add debug uart used by rk3288

[Heiko Stübner]

The uarts on rk3288 are still compatible with the dw_8250, but located
at a different position and need DEBUG_UART_8250_WORD enabled.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/Kconfig.debug | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 8f90595..f68def0 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -613,6 +613,14 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on Rockchip based platforms.
 
+	config DEBUG_RK32_UART2
+		bool "Kernel low-level debugging messages via Rockchip RK32 UART2"
+		depends on ARCH_ROCKCHIP
+		select DEBUG_UART_8250
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on Rockchip RK32xx based platforms.
+
 	config DEBUG_S3C_UART0
 		depends on PLAT_SAMSUNG
 		select DEBUG_EXYNOS_UART if ARCH_EXYNOS
@@ -1096,6 +1104,7 @@ config DEBUG_UART_PHYS
 	default 0xf991e000 if DEBUG_QCOM_UARTDM
 	default 0xfcb00000 if DEBUG_HI3620_UART
 	default 0xfe800000 if ARCH_IOP32X
+	default 0xff690000 if DEBUG_RK32_UART2
 	default 0xffc02000 if DEBUG_SOCFPGA_UART
 	default 0xffd82340 if ARCH_IOP13XX
 	default 0xfff36000 if DEBUG_HIGHBANK_UART
@@ -1152,6 +1161,7 @@ config DEBUG_UART_VIRT
 	default 0xfec02000 if DEBUG_SOCFPGA_UART
 	default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE
 	default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
+	default 0xfec90000 if DEBUG_RK32_UART2
 	default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
 	default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
 	default 0xfed12000 if ARCH_KIRKWOOD
@@ -1186,7 +1196,7 @@ config DEBUG_UART_8250_WORD
 		ARCH_KEYSTONE || \
 		DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
 		DEBUG_DAVINCI_DA8XX_UART2 || \
-		DEBUG_BCM_KONA_UART
+		DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
 
 config DEBUG_UART_8250_FLOW_CONTROL
 	bool "Enable flow control for 8250 UART"
-- 
1.9.0

[PATCH 3/6] ARM: Kconfig: set default gpio number for rockchip SoCs

[Heiko Stübner]

The new rk3288 needs a bigger gpio space, as it has 9 gpio banks.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 87b63fd..8d1dee0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1574,6 +1574,7 @@ config ARCH_NR_GPIO
 	default 416 if ARCH_SUNXI
 	default 392 if ARCH_U8500
 	default 352 if ARCH_VT8500
+	default 288 if ARCH_ROCKCHIP
 	default 264 if MACH_H4700
 	default 0
 	help
-- 
1.9.0

[PATCH 4/6] ARM: rockchip: enable support for RK3288 SoCs

[Heiko Stübner]

Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/mach-rockchip/Kconfig    | 1 +
 arch/arm/mach-rockchip/rockchip.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index e4564c2..d168669 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -6,6 +6,7 @@ config ARCH_ROCKCHIP
 	select ARCH_REQUIRE_GPIOLIB
 	select ARM_GIC
 	select CACHE_L2X0
+	select HAVE_ARM_ARCH_TIMER
 	select HAVE_ARM_SCU if SMP
 	select HAVE_ARM_TWD if SMP
 	select DW_APB_TIMER_OF
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 968cc34..8ab9e0e 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -29,6 +29,7 @@ static const char * const rockchip_board_dt_compat[] = {
 	"rockchip,rk3066a",
 	"rockchip,rk3066b",
 	"rockchip,rk3188",
+	"rockchip,rk3288",
 	NULL,
 };
 
-- 
1.9.0

[PATCH 5/6] ARM: dts: rockchip: add core rk3288 dtsi

[Heiko Stübner]

Node definitions shared by all rk3288 based boards.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3288.dtsi | 561 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 561 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3288.dtsi

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
new file mode 100644
index 0000000..6e36cec
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -0,0 +1,561 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a12";
+			reg = <0x500>;
+		};
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a12";
+			reg = <0x501>;
+		};
+		cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a12";
+			reg = <0x502>;
+		};
+		cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a12";
+			reg = <0x503>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		xin24m: xin24m {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			#clock-cells = <0>;
+		};
+
+		architected-timer {
+			compatible = "arm,armv7-timer";
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			clock-frequency = <24000000>;
+		};
+
+		gic: interrupt-controller at ffc01000 {
+			compatible = "arm,gic-400";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+
+			reg = <0xffc01000 0x1000>,
+			      <0xffc02000 0x1000>,
+			      <0xffc04000 0x2000>,
+			      <0xffc06000 0x2000>;
+			interrupts = <GIC_PPI 9 0xf04>;
+		};
+
+		pmu: pmu at ff730000 {
+			compatible = "syscon";
+			reg = <0xff730000 0x100>;
+		};
+
+		sgrf: syscon at ff740000 {
+			compatible = "syscon";
+			reg = <0xff740000 0x1000>;
+		};
+
+		cru: cru at ff760000 {
+			compatible = "rockchip,rk3288-cru";
+			reg = <0xff760000 0x1000>;
+			rockchip,grf = <&grf>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		grf: syscon at ff770000 {
+			compatible = "syscon";
+			reg = <0xff770000 0x1000>;
+		};
+
+		pinctrl: pinctrl at ff770000 {
+			compatible = "rockchip,rk3288-pinctrl";
+			rockchip,grf = <&grf>;
+			rockchip,pmu = <&pmu>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			gpio0: gpio0 at ff750000 {
+				compatible = "rockchip,gpio-bank";
+				reg =	<0xff750000 0x100>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO0>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio1: gpio1 at ff780000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff780000 0x100>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO1>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio2 at ff790000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff790000 0x100>;
+				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO2>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio3 at ff7a0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7a0000 0x100>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO3>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio4 at ff7b0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7b0000 0x100>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO4>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio5: gpio5 at ff7c0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7c0000 0x100>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO5>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio6: gpio6 at ff7d0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7d0000 0x100>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO6>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio7: gpio7 at ff7e0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7e0000 0x100>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO7>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio8: gpio8 at ff7f0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7f0000 0x100>;
+				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO8>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			pcfg_pull_up: pcfg_pull_up {
+				bias-pull-up;
+			};
+
+			pcfg_pull_down: pcfg_pull_down {
+				bias-pull-down;
+			};
+
+			pcfg_pull_none: pcfg_pull_none {
+				bias-disable;
+			};
+
+			i2c0 {
+				i2c0_xfer: i2c0-xfer {
+					rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
+							<0 16 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c1 {
+				i2c1_xfer: i2c1-xfer {
+					rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
+							<8 5 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c2 {
+				i2c2_xfer: i2c2-xfer {
+					rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
+							<6 10 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c3 {
+				i2c3_xfer: i2c3-xfer {
+					rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
+							<2 17 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c4 {
+				i2c4_xfer: i2c4-xfer {
+					rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
+							<7 18 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c5 {
+				i2c5_xfer: i2c5-xfer {
+					rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
+							<7 20 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			sdmmc {
+				sdmmc_clk: sdmmc-clk {
+					rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				sdmmc_cmd: sdmmc-cmd {
+					rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
+				};
+
+				sdmmc_cd: sdmcc-cd {
+					rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
+				};
+
+				sdmmc_bus1: sdmmc-bus1 {
+					rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
+				};
+
+				sdmmc_bus4: sdmmc-bus4 {
+					rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
+							<6 17 RK_FUNC_1 &pcfg_pull_up>,
+							<6 18 RK_FUNC_1 &pcfg_pull_up>,
+							<6 19 RK_FUNC_1 &pcfg_pull_up>;
+				};
+			};
+
+			emmc {
+				emmc_clk: emmc-clk {
+					rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
+				};
+
+				emmc_cmd: emmc-cmd {
+					rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
+				};
+
+				emmc_pwr: emmc-pwr {
+					rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
+				};
+
+				emmc_bus1: emmc-bus1 {
+					rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
+				};
+
+				emmc_bus4: emmc-bus4 {
+					rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
+							<3 1 RK_FUNC_2 &pcfg_pull_up>,
+							<3 2 RK_FUNC_2 &pcfg_pull_up>,
+							<3 3 RK_FUNC_2 &pcfg_pull_up>;
+				};
+
+				emmc_bus8: emmc-bus8 {
+					rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
+							<3 1 RK_FUNC_2 &pcfg_pull_up>,
+							<3 2 RK_FUNC_2 &pcfg_pull_up>,
+							<3 3 RK_FUNC_2 &pcfg_pull_up>,
+							<3 4 RK_FUNC_2 &pcfg_pull_up>,
+							<3 5 RK_FUNC_2 &pcfg_pull_up>,
+							<3 6 RK_FUNC_2 &pcfg_pull_up>,
+							<3 7 RK_FUNC_2 &pcfg_pull_up>;
+				};
+			};
+
+			uart0 {
+				uart0_xfer: uart0-xfer {
+					rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
+							<4 17 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart0_cts: uart0-cts {
+					rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart0_rts: uart0-rts {
+					rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			uart1 {
+				uart1_xfer: uart1-xfer {
+					rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
+							<5 9 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart1_cts: uart1-cts {
+					rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart1_rts: uart1-rts {
+					rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			uart2 {
+				uart2_xfer: uart2-xfer {
+					rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
+							<7 23 RK_FUNC_1 &pcfg_pull_none>;
+				};
+				/* no rts / cts for uart2 */
+			};
+
+			uart3 {
+				uart3_xfer: uart3-xfer {
+					rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
+							<7 8 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart3_cts: uart3-cts {
+					rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart3_rts: uart3-rts {
+					rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			uart4 {
+				uart4_xfer: uart4-xfer {
+					rockchip,pins = <5 12 3 &pcfg_pull_up>,
+							<5 13 3 &pcfg_pull_none>;
+				};
+
+				uart4_cts: uart4-cts {
+					rockchip,pins = <5 14 3 &pcfg_pull_none>;
+				};
+
+				uart4_rts: uart4-rts {
+					rockchip,pins = <5 15 3 &pcfg_pull_none>;
+				};
+			};
+		};
+
+		i2c0: i2c at ff650000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff650000 0x1000>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C0>;
+
+			status = "disabled";
+		};
+
+		i2c1: i2c at ff140000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff140000 0x1000>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C1>;
+
+			status = "disabled";
+		};
+
+		i2c2: i2c at ff660000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff660000 0x1000>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C2>;
+
+			status = "disabled";
+		};
+
+		i2c3: i2c at ff150000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff150000 0x1000>;
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C3>;
+
+			status = "disabled";
+		};
+
+		i2c4: i2c at ff160000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff160000 0x1000>;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C4>;
+
+			status = "disabled";
+		};
+
+		i2c5: i2c at ff170000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff170000 0x1000>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C5>;
+
+			status = "disabled";
+		};
+
+		watchdog at ff800000 {
+			compatible = "snps,dw-wdt";
+			reg = <0xff800000 0x100>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart0: serial at ff180000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff180000 0x100>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart1: serial at ff190000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff190000 0x100>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: serial at ff690000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff690000 0x100>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_xfer>;
+		};
+
+		uart3: serial at ff1b0000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff1b0000 0x100>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart4: serial at ff1c0000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff1c0000 0x100>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
-- 
1.9.0

[PATCH 6/6] ARM: dts: add rk3288 evaluation board

[Heiko Stübner]

There exist 2 variants using either the act8846 or rk808 as pmic, while the
rest of the board stays the same.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3288-evb-act8846.dts | 136 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/rk3288-evb-rk808.dts   |  19 +++++
 arch/arm/boot/dts/rk3288-evb.dtsi        |  77 +++++++++++++++++
 3 files changed, 232 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3288-evb-act8846.dts
 create mode 100644 arch/arm/boot/dts/rk3288-evb-rk808.dts
 create mode 100644 arch/arm/boot/dts/rk3288-evb.dtsi

diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
new file mode 100644
index 0000000..9b1ef03
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -0,0 +1,136 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "rk3288-evb.dtsi"
+
+/ {
+	compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
+};
+
+&i2c0 {
+	hym8563 at 51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+
+		#clock-cells = <0>;
+		clock-output-names = "xin32k";
+	};
+
+	act8846: act8846 at 5a {
+		compatible = "active-semi,act8846";
+		reg = <0x5a>;
+		status = "okay";
+	};
+};
+
+&act8846 {
+	regulators {
+		vcc_ddr: REG1 {
+			regulator-name = "VCC_DDR";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-always-on;
+		};
+
+		vcc_io: REG2 {
+			regulator-name = "VCC_IO";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vdd_log: REG3 {
+			regulator-name = "VDD_LOG";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-always-on;
+		};
+
+		vcc_20: REG4 {
+			regulator-name = "VCC_20";
+			regulator-min-microvolt = <2000000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-always-on;
+		};
+
+		vccio_sd: REG5 {
+			regulator-name = "VCCIO_SD";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vdd10_lcd: REG6 {
+			regulator-name = "VDD10_LCD";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-always-on;
+		};
+
+		vcca_codec: REG7 {
+			regulator-name = "VCCA_CODEC";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vcca_tp: REG8 {
+			regulator-name = "VCCA_TP";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vccio_pmu: REG9 {
+			regulator-name = "VCCIO_PMU";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vdd_10: REG10 {
+			regulator-name = "VDD_10";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-always-on;
+		};
+
+		vcc_18: REG11 {
+			regulator-name = "VCC_18";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		vcc18_lcd: REG12 {
+			regulator-name = "VCC18_LCD";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&pinctrl {
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
new file mode 100644
index 0000000..c168cb2
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -0,0 +1,19 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "rk3288-evb.dtsi"
+
+/ {
+	compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
+
+};
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
new file mode 100644
index 0000000..ff642d4
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -0,0 +1,77 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "rk3288.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	memory {
+		reg = <0x0 0x80000000>;
+	};
+
+	soc {
+		gpio-keys {
+			compatible = "gpio-keys";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			autorepeat;
+
+			button at 0 {
+				gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+				linux,code = <116>;
+				label = "GPIO Key Power";
+				linux,input-type = <1>;
+				gpio-key,wakeup = <1>;
+				debounce-interval = <100>;
+			};
+		};
+
+		i2c0: i2c at ff650000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_xfer>;
+			status = "okay";
+		};
+
+		watchdog at ff800000 {
+			status = "okay";
+		};
+
+		serial at ff180000 {
+			status = "okay";
+		};
+
+		serial at ff190000 {
+			status = "okay";
+		};
+
+		uart2: serial at ff690000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_xfer>;
+			status = "okay";
+		};
+
+		uart3: serial at ff1b0000 {
+			status = "okay";
+		};
+
+		uart4: serial at ff1c0000 {
+			status = "okay";
+		};
+	};
+};
-- 
1.9.0

[PATCH 5/6] ARM: dts: rockchip: add core rk3288 dtsi

[Doug Anderson]

Heiko,

On Tue, Jul 15, 2014 at 4:02 PM, Heiko St?bner <heiko@sntech.de> wrote:
> +       soc {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "simple-bus";
> +               ranges;

I haven't had time to do a full review, but I believe "soc" grouping
is not suggested.  See <http://patchwork.ozlabs.org/patch/323194/>

-Doug

[PATCH 5/6] ARM: dts: rockchip: add core rk3288 dtsi

[Olof Johansson]

Hi,

Bunch-o-nits below.

On Wed, Jul 16, 2014 at 01:02:20AM +0200, Heiko St?bner wrote:
> Node definitions shared by all rk3288 based boards.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/arm/boot/dts/rk3288.dtsi | 561 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 561 insertions(+)
>  create mode 100644 arch/arm/boot/dts/rk3288.dtsi
> 
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> new file mode 100644
> index 0000000..6e36cec
> --- /dev/null
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -0,0 +1,561 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/clock/rk3288-cru.h>
> +#include "skeleton.dtsi"
> +
> +/ {
> +	compatible = "rockchip,rk3288";
> +
> +	interrupt-parent = <&gic>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu at 0 {

Unit address and reg should be the same. So this should be @500 (or reg 0, but
I don't think that's what you want).

> +			device_type = "cpu";
> +			compatible = "arm,cortex-a12";
> +			reg = <0x500>;
> +		};
> +		cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a12";
> +			reg = <0x501>;
> +		};
> +		cpu at 2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a12";
> +			reg = <0x502>;
> +		};
> +		cpu at 3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a12";
> +			reg = <0x503>;
> +		};
> +	};
> +
> +	soc {

As Doug mentioned, this isn't how we tend to do it any more (unless all devices
are physically on a bus, but then it should probably be named something else
than 'soc').

> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		xin24m: xin24m {
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		architected-timer {

Most other platforms just call this "timer".

> +			compatible = "arm,armv7-timer";
> +			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +			clock-frequency = <24000000>;
> +		};
> +
> +		gic: interrupt-controller at ffc01000 {
> +			compatible = "arm,gic-400";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			#address-cells = <0>;
> +
> +			reg = <0xffc01000 0x1000>,
> +			      <0xffc02000 0x1000>,
> +			      <0xffc04000 0x2000>,
> +			      <0xffc06000 0x2000>;
> +			interrupts = <GIC_PPI 9 0xf04>;
> +		};
> +
> +		pmu: pmu at ff730000 {
> +			compatible = "syscon";
> +			reg = <0xff730000 0x100>;
> +		};

You should consider sorting entries based on address. That way, as you add new
entries over time, you'll have fewer conflicts than if they're all appended
instead.

> +
> +		sgrf: syscon at ff740000 {
> +			compatible = "syscon";
> +			reg = <0xff740000 0x1000>;
> +		};
> +
> +		cru: cru at ff760000 {

"cru"? The node name is usually something labelling the type of device
("clock-controller")?

> +			compatible = "rockchip,rk3288-cru";
> +			reg = <0xff760000 0x1000>;
> +			rockchip,grf = <&grf>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		grf: syscon at ff770000 {
> +			compatible = "syscon";

This should probably have a more precise compatible than _just_ syscon.

> +			reg = <0xff770000 0x1000>;
> +		};
> +
> +		pinctrl: pinctrl at ff770000 {

If the node doesn't have a reg entry then it shouldn't have a unit address.

> +			compatible = "rockchip,rk3288-pinctrl";
> +			rockchip,grf = <&grf>;
> +			rockchip,pmu = <&pmu>;
> +
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			gpio0: gpio0 at ff750000 {
> +				compatible = "rockchip,gpio-bank";
> +				reg =	<0xff750000 0x100>;
> +				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cru PCLK_GPIO0>;
> +
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio1: gpio1 at ff780000 {
> +				compatible = "rockchip,gpio-bank";
> +				reg = <0xff780000 0x100>;
> +				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cru PCLK_GPIO1>;
> +
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio2: gpio2 at ff790000 {
> +				compatible = "rockchip,gpio-bank";
> +				reg = <0xff790000 0x100>;
> +				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cru PCLK_GPIO2>;
> +
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio3: gpio3 at ff7a0000 {
> +				compatible = "rockchip,gpio-bank";
> +				reg = <0xff7a0000 0x100>;
> +				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cru PCLK_GPIO3>;
> +
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio4: gpio4 at ff7b0000 {
> +				compatible = "rockchip,gpio-bank";
> +				reg = <0xff7b0000 0x100>;
> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cru PCLK_GPIO4>;
> +
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio5: gpio5 at ff7c0000 {
> +				compatible = "rockchip,gpio-bank";
> +				reg = <0xff7c0000 0x100>;
> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cru PCLK_GPIO5>;
> +
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio6: gpio6 at ff7d0000 {
> +				compatible = "rockchip,gpio-bank";
> +				reg = <0xff7d0000 0x100>;
> +				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cru PCLK_GPIO6>;
> +
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio7: gpio7 at ff7e0000 {
> +				compatible = "rockchip,gpio-bank";
> +				reg = <0xff7e0000 0x100>;
> +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cru PCLK_GPIO7>;
> +
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio8: gpio8 at ff7f0000 {
> +				compatible = "rockchip,gpio-bank";
> +				reg = <0xff7f0000 0x100>;
> +				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cru PCLK_GPIO8>;
> +
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			pcfg_pull_up: pcfg_pull_up {
> +				bias-pull-up;
> +			};
> +
> +			pcfg_pull_down: pcfg_pull_down {
> +				bias-pull-down;
> +			};
> +
> +			pcfg_pull_none: pcfg_pull_none {
> +				bias-disable;
> +			};
> +
> +			i2c0 {
> +				i2c0_xfer: i2c0-xfer {
> +					rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
> +							<0 16 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +			};
> +
> +			i2c1 {
> +				i2c1_xfer: i2c1-xfer {
> +					rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
> +							<8 5 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +			};
> +
> +			i2c2 {
> +				i2c2_xfer: i2c2-xfer {
> +					rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
> +							<6 10 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +			};
> +
> +			i2c3 {
> +				i2c3_xfer: i2c3-xfer {
> +					rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
> +							<2 17 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +			};
> +
> +			i2c4 {
> +				i2c4_xfer: i2c4-xfer {
> +					rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
> +							<7 18 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +			};
> +
> +			i2c5 {
> +				i2c5_xfer: i2c5-xfer {
> +					rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
> +							<7 20 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +			};
> +
> +			sdmmc {
> +				sdmmc_clk: sdmmc-clk {
> +					rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +
> +				sdmmc_cmd: sdmmc-cmd {
> +					rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
> +				};
> +
> +				sdmmc_cd: sdmcc-cd {
> +					rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
> +				};
> +
> +				sdmmc_bus1: sdmmc-bus1 {
> +					rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
> +				};
> +
> +				sdmmc_bus4: sdmmc-bus4 {
> +					rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
> +							<6 17 RK_FUNC_1 &pcfg_pull_up>,
> +							<6 18 RK_FUNC_1 &pcfg_pull_up>,
> +							<6 19 RK_FUNC_1 &pcfg_pull_up>;
> +				};
> +			};
> +
> +			emmc {
> +				emmc_clk: emmc-clk {
> +					rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
> +				};
> +
> +				emmc_cmd: emmc-cmd {
> +					rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
> +				};
> +
> +				emmc_pwr: emmc-pwr {
> +					rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
> +				};
> +
> +				emmc_bus1: emmc-bus1 {
> +					rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
> +				};
> +
> +				emmc_bus4: emmc-bus4 {
> +					rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 1 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 2 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 3 RK_FUNC_2 &pcfg_pull_up>;
> +				};
> +
> +				emmc_bus8: emmc-bus8 {
> +					rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 1 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 2 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 3 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 4 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 5 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 6 RK_FUNC_2 &pcfg_pull_up>,
> +							<3 7 RK_FUNC_2 &pcfg_pull_up>;
> +				};
> +			};
> +
> +			uart0 {
> +				uart0_xfer: uart0-xfer {
> +					rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
> +							<4 17 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +
> +				uart0_cts: uart0-cts {
> +					rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +
> +				uart0_rts: uart0-rts {
> +					rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +			};
> +
> +			uart1 {
> +				uart1_xfer: uart1-xfer {
> +					rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
> +							<5 9 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +
> +				uart1_cts: uart1-cts {
> +					rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +
> +				uart1_rts: uart1-rts {
> +					rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +			};
> +
> +			uart2 {
> +				uart2_xfer: uart2-xfer {
> +					rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
> +							<7 23 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +				/* no rts / cts for uart2 */
> +			};
> +
> +			uart3 {
> +				uart3_xfer: uart3-xfer {
> +					rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
> +							<7 8 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +
> +				uart3_cts: uart3-cts {
> +					rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +
> +				uart3_rts: uart3-rts {
> +					rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
> +				};
> +			};
> +
> +			uart4 {
> +				uart4_xfer: uart4-xfer {
> +					rockchip,pins = <5 12 3 &pcfg_pull_up>,
> +							<5 13 3 &pcfg_pull_none>;
> +				};
> +
> +				uart4_cts: uart4-cts {
> +					rockchip,pins = <5 14 3 &pcfg_pull_none>;
> +				};
> +
> +				uart4_rts: uart4-rts {
> +					rockchip,pins = <5 15 3 &pcfg_pull_none>;
> +				};
> +			};
> +		};
> +
> +		i2c0: i2c at ff650000 {
> +			compatible = "rockchip,rk3288-i2c";
> +			reg = <0xff650000 0x1000>;
> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			clock-names = "i2c";
> +			clocks = <&cru PCLK_I2C0>;
> +
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c at ff140000 {
> +			compatible = "rockchip,rk3288-i2c";
> +			reg = <0xff140000 0x1000>;
> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			clock-names = "i2c";
> +			clocks = <&cru PCLK_I2C1>;
> +
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c at ff660000 {
> +			compatible = "rockchip,rk3288-i2c";
> +			reg = <0xff660000 0x1000>;
> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			clock-names = "i2c";
> +			clocks = <&cru PCLK_I2C2>;
> +
> +			status = "disabled";
> +		};
> +
> +		i2c3: i2c at ff150000 {
> +			compatible = "rockchip,rk3288-i2c";
> +			reg = <0xff150000 0x1000>;
> +			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			clock-names = "i2c";
> +			clocks = <&cru PCLK_I2C3>;
> +
> +			status = "disabled";
> +		};
> +
> +		i2c4: i2c at ff160000 {
> +			compatible = "rockchip,rk3288-i2c";
> +			reg = <0xff160000 0x1000>;
> +			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			clock-names = "i2c";
> +			clocks = <&cru PCLK_I2C4>;
> +
> +			status = "disabled";
> +		};
> +
> +		i2c5: i2c at ff170000 {
> +			compatible = "rockchip,rk3288-i2c";
> +			reg = <0xff170000 0x1000>;
> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			clock-names = "i2c";
> +			clocks = <&cru PCLK_I2C5>;
> +
> +			status = "disabled";
> +		};
> +
> +		watchdog at ff800000 {
> +			compatible = "snps,dw-wdt";

Same here, you might want a more specific compatible as the higher-priority
one.

> +			reg = <0xff800000 0x100>;
> +			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		uart0: serial at ff180000 {
> +			compatible = "snps,dw-apb-uart";

And again w.r.t compatible (I'll stop pointing them out now).

> +			reg = <0xff180000 0x100>;
> +			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> +			clock-names = "baudclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart1: serial at ff190000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0xff190000 0x100>;
> +			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
> +			clock-names = "baudclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart2: serial at ff690000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0xff690000 0x100>;
> +			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
> +			clock-names = "baudclk", "apb_pclk";
> +			status = "disabled";
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&uart2_xfer>;
> +		};
> +
> +		uart3: serial at ff1b0000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0xff1b0000 0x100>;
> +			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
> +			clock-names = "baudclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart4: serial at ff1c0000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0xff1c0000 0x100>;
> +			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
> +			clock-names = "baudclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +	};
> +};
> -- 
> 1.9.0
> 
> 

[PATCH 1/6] dt-bindings: arm: add arm,cortex-a12 cpu compatible property

[Olof Johansson]

On Wed, Jul 16, 2014 at 12:59:33AM +0200, Heiko St?bner wrote:
> This is necessary for the new RK3288 soc.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 1fe72a0..620a1a8 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -152,6 +152,7 @@ nodes to be present and contain the properties described below.
>  			    "arm,cortex-a7"
>  			    "arm,cortex-a8"
>  			    "arm,cortex-a9"
> +			    "arm,cortex-a12"
>  			    "arm,cortex-a15"
>  			    "arm,cortex-a53"

You might as well add -a17 while you're at it, since it's an announced part
from ARM.


-Olof

[PATCH 6/6] ARM: dts: add rk3288 evaluation board

[Olof Johansson]

Hi,

This mostly looks good, with a couple of comments below.

On Wed, Jul 16, 2014 at 01:02:58AM +0200, Heiko St?bner wrote:
> +&i2c0 {
> +	hym8563 at 51 {
> +		compatible = "haoyu,hym8563";
> +		reg = <0x51>;
> +
> +		interrupt-parent = <&gpio0>;
> +		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
> +
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&hym8563_int>;
> +
> +		#clock-cells = <0>;
> +		clock-output-names = "xin32k";
> +	};
> +
> +	act8846: act8846 at 5a {
> +		compatible = "active-semi,act8846";
> +		reg = <0x5a>;
> +		status = "okay";
> +	};
> +};
> +
> +&act8846 {

This is slightly odd since you're defining the node just above, you could just
add the regulators right there.

> +	regulators {
> +		vcc_ddr: REG1 {
> +			regulator-name = "VCC_DDR";
> +			regulator-min-microvolt = <1200000>;
> +			regulator-max-microvolt = <1200000>;
> +			regulator-always-on;
> +		};
> +
> +		vcc_io: REG2 {
> +			regulator-name = "VCC_IO";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +		};
> +
> +		vdd_log: REG3 {
> +			regulator-name = "VDD_LOG";
> +			regulator-min-microvolt = <1000000>;
> +			regulator-max-microvolt = <1000000>;
> +			regulator-always-on;
> +		};
> +
> +		vcc_20: REG4 {
> +			regulator-name = "VCC_20";
> +			regulator-min-microvolt = <2000000>;
> +			regulator-max-microvolt = <2000000>;
> +			regulator-always-on;
> +		};
> +
> +		vccio_sd: REG5 {
> +			regulator-name = "VCCIO_SD";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +		};
> +
> +		vdd10_lcd: REG6 {
> +			regulator-name = "VDD10_LCD";
> +			regulator-min-microvolt = <1000000>;
> +			regulator-max-microvolt = <1000000>;
> +			regulator-always-on;
> +		};
> +
> +		vcca_codec: REG7 {
> +			regulator-name = "VCCA_CODEC";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +		};
> +
> +		vcca_tp: REG8 {
> +			regulator-name = "VCCA_TP";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +		};
> +
> +		vccio_pmu: REG9 {
> +			regulator-name = "VCCIO_PMU";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +		};
> +
> +		vdd_10: REG10 {
> +			regulator-name = "VDD_10";
> +			regulator-min-microvolt = <1000000>;
> +			regulator-max-microvolt = <1000000>;
> +			regulator-always-on;
> +		};
> +
> +		vcc_18: REG11 {
> +			regulator-name = "VCC_18";
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +			regulator-always-on;
> +		};
> +
> +		vcc18_lcd: REG12 {
> +			regulator-name = "VCC18_LCD";
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +			regulator-always-on;
> +		};
> +	};
> +};
> +
> +&pinctrl {
> +	hym8563 {
> +		hym8563_int: hym8563-int {
> +			rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
> new file mode 100644
> index 0000000..c168cb2
> --- /dev/null
> +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
> @@ -0,0 +1,19 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +#include "rk3288-evb.dtsi"
> +
> +/ {
> +	compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
> +
> +};

No rk808 node? Or adding that once the driver is sorted out?

> diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
> new file mode 100644
> index 0000000..ff642d4
> --- /dev/null
> +++ b/arch/arm/boot/dts/rk3288-evb.dtsi
> @@ -0,0 +1,77 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include "rk3288.dtsi"
> +
> +/ {
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +	};
> +
> +	memory {
> +		reg = <0x0 0x80000000>;
> +	};
> +
> +	soc {
> +		gpio-keys {

I'd recommend doing all of these with &-references instead to avoid having to
revisit this if/when the tree topography changes w.r.t. the 'soc' node. Also,
the gpio-keys should be on the top level.

> +			compatible = "gpio-keys";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			autorepeat;
> +
> +			button at 0 {
> +				gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
> +				linux,code = <116>;
> +				label = "GPIO Key Power";
> +				linux,input-type = <1>;
> +				gpio-key,wakeup = <1>;
> +				debounce-interval = <100>;
> +			};
> +		};
> +
> +		i2c0: i2c at ff650000 {
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c0_xfer>;
> +			status = "okay";
> +		};
> +
> +		watchdog at ff800000 {
> +			status = "okay";
> +		};
> +
> +		serial at ff180000 {
> +			status = "okay";
> +		};
> +
> +		serial at ff190000 {
> +			status = "okay";
> +		};
> +
> +		uart2: serial at ff690000 {
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&uart2_xfer>;
> +			status = "okay";
> +		};
> +
> +		uart3: serial at ff1b0000 {
> +			status = "okay";
> +		};
> +
> +		uart4: serial at ff1c0000 {
> +			status = "okay";
> +		};
> +	};
> +};


-Olof

[PATCH 2/6] ARM: rockchip: add debug uart used by rk3288

[Doug Anderson]

Heiko,

On Tue, Jul 15, 2014 at 4:00 PM, Heiko St?bner <heiko@sntech.de> wrote:
> The uarts on rk3288 are still compatible with the dw_8250, but located
> at a different position and need DEBUG_UART_8250_WORD enabled.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/arm/Kconfig.debug | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 8f90595..f68def0 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -613,6 +613,14 @@ choice
>                   Say Y here if you want kernel low-level debugging support
>                   on Rockchip based platforms.
>
> +       config DEBUG_RK32_UART2

It's slightly confusing that you didn't rename the old "DEBUG_RK3X_UART2".

Other than that:

Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>

[PATCH 3/6] ARM: Kconfig: set default gpio number for rockchip SoCs

[Doug Anderson]

Heiko,

On Tue, Jul 15, 2014 at 4:01 PM, Heiko St?bner <heiko@sntech.de> wrote:
> The new rk3288 needs a bigger gpio space, as it has 9 gpio banks.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/arm/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 87b63fd..8d1dee0 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1574,6 +1574,7 @@ config ARCH_NR_GPIO
>         default 416 if ARCH_SUNXI
>         default 392 if ARCH_U8500
>         default 352 if ARCH_VT8500
> +       default 288 if ARCH_ROCKCHIP

Looks reasonable.  9 banks of 32 and that matches what's in the pinmux driver.

Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>

[PATCH 1/6] dt-bindings: arm: add arm,cortex-a12 cpu compatible property

[Mark Rutland]

On Wed, Jul 16, 2014 at 01:56:16AM +0100, Olof Johansson wrote:
> On Wed, Jul 16, 2014 at 12:59:33AM +0200, Heiko St?bner wrote:
> > This is necessary for the new RK3288 soc.
> > 
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> >  Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> > index 1fe72a0..620a1a8 100644
> > --- a/Documentation/devicetree/bindings/arm/cpus.txt
> > +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> > @@ -152,6 +152,7 @@ nodes to be present and contain the properties described below.
> >  			    "arm,cortex-a7"
> >  			    "arm,cortex-a8"
> >  			    "arm,cortex-a9"
> > +			    "arm,cortex-a12"
> >  			    "arm,cortex-a15"
> >  			    "arm,cortex-a53"
> 
> You might as well add -a17 while you're at it, since it's an announced part
> from ARM.

Yes please!

For said patch with both strings:

Acked-by: Mark Rutland <mark.rutland@arm.com>

Thanks,
Mark.

[PATCH 2/6] ARM: rockchip: add debug uart used by rk3288

[Heiko Stübner]

Am Dienstag, 15. Juli 2014, 21:13:10 schrieb Doug Anderson:
> Heiko,
> 
> On Tue, Jul 15, 2014 at 4:00 PM, Heiko St?bner <heiko@sntech.de> wrote:
> > The uarts on rk3288 are still compatible with the dw_8250, but located
> > at a different position and need DEBUG_UART_8250_WORD enabled.
> > 
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> > 
> >  arch/arm/Kconfig.debug | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> > index 8f90595..f68def0 100644
> > --- a/arch/arm/Kconfig.debug
> > +++ b/arch/arm/Kconfig.debug
> > @@ -613,6 +613,14 @@ choice
> > 
> >                   Say Y here if you want kernel low-level debugging
> >                   support
> >                   on Rockchip based platforms.
> > 
> > +       config DEBUG_RK32_UART2
> 
> It's slightly confusing that you didn't rename the old "DEBUG_RK3X_UART2".

My problem is, to what :-) ... DEBUG_RK30_UART2 ?

RK30xx and RK31xx share these, but I guess at least the description should be 
adapted.


> 
> Other than that:
> 
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>

[PATCH 2/6] ARM: rockchip: add debug uart used by rk3288

[Doug Anderson]

Heiko,

On Wed, Jul 16, 2014 at 2:11 AM, Heiko St?bner <heiko@sntech.de> wrote:
> Am Dienstag, 15. Juli 2014, 21:13:10 schrieb Doug Anderson:
>> Heiko,
>>
>> On Tue, Jul 15, 2014 at 4:00 PM, Heiko St?bner <heiko@sntech.de> wrote:
>> > The uarts on rk3288 are still compatible with the dw_8250, but located
>> > at a different position and need DEBUG_UART_8250_WORD enabled.
>> >
>> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> > ---
>> >
>> >  arch/arm/Kconfig.debug | 12 +++++++++++-
>> >  1 file changed, 11 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
>> > index 8f90595..f68def0 100644
>> > --- a/arch/arm/Kconfig.debug
>> > +++ b/arch/arm/Kconfig.debug
>> > @@ -613,6 +613,14 @@ choice
>> >
>> >                   Say Y here if you want kernel low-level debugging
>> >                   support
>> >                   on Rockchip based platforms.
>> >
>> > +       config DEBUG_RK32_UART2
>>
>> It's slightly confusing that you didn't rename the old "DEBUG_RK3X_UART2".
>
> My problem is, to what :-) ... DEBUG_RK30_UART2 ?
>
> RK30xx and RK31xx share these, but I guess at least the description should be
> adapted.

Yeah, trying to get these things right is an impossible task.  The
only thing I've ever seen that's sane is to just name things after the
first person in the code base to use them rather than trying to guess
ahead of time how similar products with similar marketing name will be
in the future.

...agree that even if you don't do the rename here that updating the
description would be nice.

-Doug

[PATCH 4/6] ARM: rockchip: enable support for RK3288 SoCs

[Doug Anderson]

Heiko,

On Tue, Jul 15, 2014 at 4:01 PM, Heiko St?bner <heiko@sntech.de> wrote:
> Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/arm/mach-rockchip/Kconfig    | 1 +
>  arch/arm/mach-rockchip/rockchip.c | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index e4564c2..d168669 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -6,6 +6,7 @@ config ARCH_ROCKCHIP
>         select ARCH_REQUIRE_GPIOLIB
>         select ARM_GIC
>         select CACHE_L2X0
> +       select HAVE_ARM_ARCH_TIMER

Do we want to think about allowing someone to enable the A9-based
Rockchip SoCs separately than the A12-based ones?  I know it doesn't
hurt to have the arch timer code present on A9 SoCs (it will figure
things out at runtime), but people trying to build an A9-based system
might not want the extra code?

Anyway, I don't feel strongly about it, so:

Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>

[PATCH 6/6] ARM: dts: add rk3288 evaluation board

[Doug Anderson]

Heiko,

On Tue, Jul 15, 2014 at 4:02 PM, Heiko St?bner <heiko@sntech.de> wrote:
> diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
> new file mode 100644
> index 0000000..c168cb2
> --- /dev/null
> +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
> @@ -0,0 +1,19 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +#include "rk3288-evb.dtsi"
> +
> +/ {
> +       compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
> +

nit: remove extra blank line?

> +};
> diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
> new file mode 100644
> index 0000000..ff642d4
> --- /dev/null
> +++ b/arch/arm/boot/dts/rk3288-evb.dtsi
> @@ -0,0 +1,77 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include "rk3288.dtsi"
> +
> +/ {
> +       aliases {
> +               serial0 = &uart0;
> +               serial1 = &uart1;
> +               serial2 = &uart2;
> +               serial3 = &uart3;
> +               serial4 = &uart4;

Can the aliases go in the main dtsi?

> +       };
> +
> +       memory {
> +               reg = <0x0 0x80000000>;
> +       };
> +
> +       soc {
> +               gpio-keys {
> +                       compatible = "gpio-keys";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       autorepeat;

I would have expected pinctrl for gpio0-5 to make sure pulls are
enabled / disabled as appropriate.

> +
> +                       button at 0 {
> +                               gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
> +                               linux,code = <116>;
> +                               label = "GPIO Key Power";
> +                               linux,input-type = <1>;
> +                               gpio-key,wakeup = <1>;
> +                               debounce-interval = <100>;
> +                       };
> +               };
> +
> +               i2c0: i2c at ff650000 {
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&i2c0_xfer>;
> +                       status = "okay";
> +               };
> +
> +               watchdog at ff800000 {
> +                       status = "okay";
> +               };
> +
> +               serial at ff180000 {
> +                       status = "okay";
> +               };
> +
> +               serial at ff190000 {
> +                       status = "okay";
> +               };
> +
> +               uart2: serial at ff690000 {
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&uart2_xfer>;

Why is this pinctrl here?

> +                       status = "okay";
> +               };

[PATCH 5/6] ARM: dts: rockchip: add core rk3288 dtsi

[Doug Anderson]

Heiko,

On Tue, Jul 15, 2014 at 4:02 PM, Heiko St?bner <heiko@sntech.de> wrote:
> +                       i2c0 {
> +                               i2c0_xfer: i2c0-xfer {
> +                                       rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
> +                                                       <0 16 RK_FUNC_1 &pcfg_pull_none>;
> +                               };
> +                       };
> +
> +                       i2c1 {
> +                               i2c1_xfer: i2c1-xfer {
> +                                       rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
> +                                                       <8 5 RK_FUNC_1 &pcfg_pull_none>;
> +                               };
> +                       };
> +
> +                       i2c2 {
> +                               i2c2_xfer: i2c2-xfer {
> +                                       rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
> +                                                       <6 10 RK_FUNC_1 &pcfg_pull_none>;
> +                               };
> +                       };
> +
> +                       i2c3 {
> +                               i2c3_xfer: i2c3-xfer {
> +                                       rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
> +                                                       <2 17 RK_FUNC_1 &pcfg_pull_none>;
> +                               };
> +                       };
> +
> +                       i2c4 {
> +                               i2c4_xfer: i2c4-xfer {
> +                                       rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
> +                                                       <7 18 RK_FUNC_1 &pcfg_pull_none>;
> +                               };
> +                       };
> +
> +                       i2c5 {
> +                               i2c5_xfer: i2c5-xfer {
> +                                       rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
> +                                                       <7 20 RK_FUNC_1 &pcfg_pull_none>;
> +                               };
> +                       };

Since there's a strong concept of numbering of i2c busses on this SoC,
could you add aliases so that they show up nicely with the right ID?

Thanks!

-Doug

[PATCH 4/6] ARM: rockchip: enable support for RK3288 SoCs

[Heiko Stübner]

Am Mittwoch, 16. Juli 2014, 12:57:21 schrieb Doug Anderson:
> Heiko,
> 
> On Tue, Jul 15, 2014 at 4:01 PM, Heiko St?bner <heiko@sntech.de> wrote:
> > Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.
> > 
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> > 
> >  arch/arm/mach-rockchip/Kconfig    | 1 +
> >  arch/arm/mach-rockchip/rockchip.c | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm/mach-rockchip/Kconfig
> > b/arch/arm/mach-rockchip/Kconfig index e4564c2..d168669 100644
> > --- a/arch/arm/mach-rockchip/Kconfig
> > +++ b/arch/arm/mach-rockchip/Kconfig
> > @@ -6,6 +6,7 @@ config ARCH_ROCKCHIP
> > 
> >         select ARCH_REQUIRE_GPIOLIB
> >         select ARM_GIC
> >         select CACHE_L2X0
> > 
> > +       select HAVE_ARM_ARCH_TIMER
> 
> Do we want to think about allowing someone to enable the A9-based
> Rockchip SoCs separately than the A12-based ones?  I know it doesn't
> hurt to have the arch timer code present on A9 SoCs (it will figure
> things out at runtime), but people trying to build an A9-based system
> might not want the extra code?
> 
> Anyway, I don't feel strongly about it, so:

I've also thought about this previously. Personally I would want to wait with 
introducing more complexity here until someone comes along with a use case.
Simply because we're talking about 7kb (stripped) for the arch-timer and 
machines with >1GB of memory.
So I'm not adverse to it, but I guess it will make more sense when more soc-
specific code lands - suspend stuff for example.


But I think we should be able to drop the dw_apb_timer altogether, as it stems 
from a time before I found the global-timer informations and all A9 SoCs 
should be able to use this one instead.




> 
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>

[PATCH 6/6] ARM: dts: add rk3288 evaluation board

[Heiko Stübner]

Am Mittwoch, 16. Juli 2014, 13:02:53 schrieb Doug Anderson:
> Heiko,
> 
> On Tue, Jul 15, 2014 at 4:02 PM, Heiko St?bner <heiko@sntech.de> wrote:
> > diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts
> > b/arch/arm/boot/dts/rk3288-evb-rk808.dts new file mode 100644
> > index 0000000..c168cb2
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
> > @@ -0,0 +1,19 @@
> > +/*
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +/dts-v1/;
> > +#include "rk3288-evb.dtsi"
> > +
> > +/ {
> > +       compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
> > +
> 
> nit: remove extra blank line?
> 
> > +};
> > diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
> > b/arch/arm/boot/dts/rk3288-evb.dtsi new file mode 100644
> > index 0000000..ff642d4
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/rk3288-evb.dtsi
> > @@ -0,0 +1,77 @@
> > +/*
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include "rk3288.dtsi"
> > +
> > +/ {
> > +       aliases {
> > +               serial0 = &uart0;
> > +               serial1 = &uart1;
> > +               serial2 = &uart2;
> > +               serial3 = &uart3;
> > +               serial4 = &uart4;
> 
> Can the aliases go in the main dtsi?
> 
> > +       };
> > +
> > +       memory {
> > +               reg = <0x0 0x80000000>;
> > +       };
> > +
> > +       soc {
> > +               gpio-keys {
> > +                       compatible = "gpio-keys";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       autorepeat;
> 
> I would have expected pinctrl for gpio0-5 to make sure pulls are
> enabled / disabled as appropriate.
> 
> > +
> > +                       button at 0 {
> > +                               gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
> > +                               linux,code = <116>;
> > +                               label = "GPIO Key Power";
> > +                               linux,input-type = <1>;
> > +                               gpio-key,wakeup = <1>;
> > +                               debounce-interval = <100>;
> > +                       };
> > +               };
> > +
> > +               i2c0: i2c at ff650000 {
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&i2c0_xfer>;
> > +                       status = "okay";
> > +               };
> > +
> > +               watchdog at ff800000 {
> > +                       status = "okay";
> > +               };
> > +
> > +               serial at ff180000 {
> > +                       status = "okay";
> > +               };
> > +
> > +               serial at ff190000 {
> > +                       status = "okay";
> > +               };
> > +
> > +               uart2: serial at ff690000 {
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&uart2_xfer>;
> 
> Why is this pinctrl here?

The other uarts also have rts/cts pins available, but optional it seems. So my 
idea was to let the boards decide which pins to use, instead of setting it in 
the soc-dtsi.

Other opinions? :-)


> 
> > +                       status = "okay";
> > +               };

[PATCH 0/6] ARM: rockchip: add initial support for rk3288

[Will Deacon]

On Tue, Jul 15, 2014 at 11:58:00PM +0100, Heiko St?bner wrote:
> This series adds the initial support for Rockchip rk3288 socs including
> debug uart and devicetree files for the rk3288 evaluation board and
> enables these boards to boot into an initramfs.
> 
> The series depends on an updated bootloader, which must start the timer
> supplying the architected timer, which we will hopefully get in the next
> days. It also depends on the patch
>     "irqchip: gic: Add binding probe for ARM GIC400"
> which will hopefully make it into the irqchip tree shortly.
> 
> 
> Heiko Stuebner (6):
>   dt-bindings: arm: add arm,cortex-a12 cpu compatible property
>   ARM: rockchip: add debug uart used by rk3288
>   ARM: Kconfig: set default gpio number for rockchip SoCs
>   ARM: rockchip: enable support for RK3288 SoCs
>   ARM: dts: rockchip: add core rk3288 dtsi
>   ARM: dts: add rk3288 evaluation board

For the series:

  Tested-by: Will Deacon <will.deacon@arm.com>

Cheers Heiko!

Will

[PATCH 4/6] ARM: rockchip: enable support for RK3288 SoCs

[Will Deacon]

On Wed, Jul 16, 2014 at 08:57:21PM +0100, Doug Anderson wrote:
> Heiko,
> 
> On Tue, Jul 15, 2014 at 4:01 PM, Heiko St?bner <heiko@sntech.de> wrote:
> > Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.
> >
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> >  arch/arm/mach-rockchip/Kconfig    | 1 +
> >  arch/arm/mach-rockchip/rockchip.c | 1 +
> >  2 files changed, 2 insertions(+)
> >
> > diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> > index e4564c2..d168669 100644
> > --- a/arch/arm/mach-rockchip/Kconfig
> > +++ b/arch/arm/mach-rockchip/Kconfig
> > @@ -6,6 +6,7 @@ config ARCH_ROCKCHIP
> >         select ARCH_REQUIRE_GPIOLIB
> >         select ARM_GIC
> >         select CACHE_L2X0
> > +       select HAVE_ARM_ARCH_TIMER
> 
> Do we want to think about allowing someone to enable the A9-based
> Rockchip SoCs separately than the A12-based ones?  I know it doesn't
> hurt to have the arch timer code present on A9 SoCs (it will figure
> things out at runtime), but people trying to build an A9-based system
> might not want the extra code?

More likely, people using the A12-based system won't want the CACHE_L2X0
code (which adds an outer_cache.sync check to wmb()).

Will