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Tue, 23 Jan 2024 03:17:04 -0800 (PST) Received: from [192.168.1.20] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id w18-20020a05600c475200b0040d2d33312csm42650785wmo.2.2024.01.23.03.17.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Jan 2024 03:17:03 -0800 (PST) Message-ID: <26b9a75c-3721-4d7a-985e-772d9f67e6d5@linaro.org> Date: Tue, 23 Jan 2024 12:17:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/9] soc: samsung: exynos-pmu: Add exynos_pmu_update/read/write APIs and SoC quirks Content-Language: en-US To: Peter Griffin , arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org References: <20240122225710.1952066-1-peter.griffin@linaro.org> <20240122225710.1952066-3-peter.griffin@linaro.org> From: Krzysztof Kozlowski Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 22/01/2024 23:57, Peter Griffin wrote: > Newer Exynos SoCs have atomic set/clear bit hardware for PMU registers as > these registers can be accessed by multiple masters. Some platforms also > protect the PMU registers for security hardening reasons so they can't be > written by normal world and are only write acessible in el3 via a SMC call. Typo? accessible? > > Add support for both of these usecases using SoC specific quirks that are > determined from the DT compatible string.> > Drivers which need to read and write PMU registers should now use these > new exynos_pmu_*() APIs instead of obtaining a regmap using > syscon_regmap_lookup_by_phandle() > > Depending on the SoC specific quirks, the exynos_pmu_*() APIs will access > the PMU register in the appropriate way. > > Signed-off-by: Peter Griffin > --- > drivers/soc/samsung/exynos-pmu.c | 209 ++++++++++++++++++++++++- > drivers/soc/samsung/exynos-pmu.h | 4 + > include/linux/soc/samsung/exynos-pmu.h | 28 ++++ > 3 files changed, 234 insertions(+), 7 deletions(-) > > diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c > index 250537d7cfd6..e9e933ede568 100644 > --- a/drivers/soc/samsung/exynos-pmu.c > +++ b/drivers/soc/samsung/exynos-pmu.c > @@ -5,6 +5,7 @@ > // > // Exynos - CPU PMU(Power Management Unit) support > > +#include > #include > #include > #include > @@ -12,29 +13,204 @@ > #include > #include > #include > +#include > > #include > #include > > #include "exynos-pmu.h" > > +/** > + * DOC: Quirk flags for different Exynos PMU IP-cores > + * > + * This driver supports multiple Exynos based SoCs, each of which might have a > + * different set of registers and features supported. > + * > + * Quirk flags described below serve the purpose of telling the driver about > + * mentioned SoC traits, and can be specified in driver data for each particular > + * supported device. > + * > + * %QUIRK_HAS_ATOMIC_BITSETHW: PMU IP has special atomic bit set/clear HW > + * to protect against PMU registers being accessed from multiple bus masters. > + * > + * %QUIRK_PMU_ALIVE_WRITE_SEC: PMU registers are *not* write accesible from > + * normal world. This is found on some SoCs as a security hardening measure. PMU > + * registers on these SoCs can only be written via a SMC call and registers are > + * checked by EL3 firmware against an allowlist before the write can procede. > + * Note: This quirk should only be set for platforms whose el3 firmware > + * implements the TENSOR_SMC_PMU_SEC_REG interface below. > + */ > + > +#define QUIRK_HAS_ATOMIC_BITSETHW BIT(0) > +#define QUIRK_PMU_ALIVE_WRITE_SEC BIT(1) > + > +#define PMUALIVE_MASK GENMASK(14, 0) > + > struct exynos_pmu_context { > struct device *dev; > const struct exynos_pmu_data *pmu_data; > + struct regmap *pmureg; > + void __iomem *pmu_base_addr; > + phys_addr_t pmu_base_pa; > + /* protect PMU reg atomic update operations */ > + spinlock_t update_lock; > }; > > -void __iomem *pmu_base_addr; > static struct exynos_pmu_context *pmu_context; > > +/* > + * Some SoCs are configured so that PMU_ALIVE registers can only be written > + * from el3. As Linux needs to write some of these registers, the following > + * SMC register read/write/read,write,modify interface is used. > + * > + * Note: This SMC interface is known to be implemented on gs101 and derivative > + * SoCs. > + */ > +#define TENSOR_SMC_PMU_SEC_REG (0x82000504) > +#define TENSOR_PMUREG_READ 0 > +#define TENSOR_PMUREG_WRITE 1 > +#define TENSOR_PMUREG_RMW 2 These are tensor specific... > + > +int set_priv_reg(phys_addr_t reg, u32 val) ...but this not... > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(TENSOR_SMC_PMU_SEC_REG, ... and this is again. Some naming should be clarified, e.g. tensor specific functions should have some prefix as well, e.g. tensor_writel(), tensor_cmpxchg() or something similar. > + reg, > + TENSOR_PMUREG_WRITE, > + val, 0, 0, 0, 0, &res); > + > + if (res.a0) > + pr_warn("%s(): SMC failed: %lu\n", __func__, res.a0); > + > + return (int)res.a0; > +} > + > +int rmw_priv_reg(phys_addr_t reg, u32 mask, u32 val) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(TENSOR_SMC_PMU_SEC_REG, > + reg, > + TENSOR_PMUREG_RMW, > + mask, val, 0, 0, 0, &res); > + > + if (res.a0) > + pr_warn("%s(): SMC failed: %lu\n", __func__, res.a0); > + > + return (int)res.a0; > +} > + > +/* > + * For SoCs that have set/clear bit hardware (as indicated by > + * QUIRK_HAS_ATOMIC_BITSETHW) this function can be used when > + * the PMU register will be accessed by multiple masters. > + * > + * For example, to set bits 13:8 in PMU reg offset 0x3e80 > + * exynos_pmu_set_bit_atomic(0x3e80, 0x3f00, 0x3f00); > + * > + * To clear bits 13:8 in PMU offset 0x3e80 > + * exynos_pmu_set_bit_atomic(0x3e80, 0x0, 0x3f00); > + */ > +static inline void exynos_pmu_set_bit_atomic(unsigned int offset, > + u32 val, u32 mask) > +{ > + unsigned long flags; > + unsigned int i; > + > + spin_lock_irqsave(&pmu_context->update_lock, flags); > + for (i = 0; i < 32; i++) { > + if (mask & BIT(i)) { > + if (val & BIT(i)) { > + offset |= 0xc000; > + pmu_raw_writel(i, offset); > + } else { > + offset |= 0x8000; > + pmu_raw_writel(i, offset); > + } > + } > + } > + spin_unlock_irqrestore(&pmu_context->update_lock, flags); > +} > + > +int exynos_pmu_update_bits(unsigned int offset, unsigned int mask, > + unsigned int val) > +{ > + if (pmu_context->pmu_data && > + pmu_context->pmu_data->quirks & QUIRK_PMU_ALIVE_WRITE_SEC) > + return rmw_priv_reg(pmu_context->pmu_base_pa + offset, > + mask, val); > + > + return regmap_update_bits(pmu_context->pmureg, offset, mask, val); > +} > +EXPORT_SYMBOL(exynos_pmu_update_bits); You need kerneldoc for all exported functions. Also, EXPORT_SYMBOL_GPL > + > void pmu_raw_writel(u32 val, u32 offset) > { > - writel_relaxed(val, pmu_base_addr + offset); > + if (pmu_context->pmu_data && > + pmu_context->pmu_data->quirks & QUIRK_PMU_ALIVE_WRITE_SEC) > + return (void)set_priv_reg(pmu_context->pmu_base_pa + offset, > + val); > + > + return writel_relaxed(val, pmu_context->pmu_base_addr + offset); > } > ... > diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h > index 1c652ffd79b4..570c6e4dc8c3 100644 > --- a/drivers/soc/samsung/exynos-pmu.h > +++ b/drivers/soc/samsung/exynos-pmu.h > @@ -25,8 +25,12 @@ struct exynos_pmu_data { > void (*pmu_init)(void); > void (*powerdown_conf)(enum sys_powerdown); > void (*powerdown_conf_extra)(enum sys_powerdown); > + u32 quirks; > }; > > +int set_priv_reg(phys_addr_t reg, u32 val); > +int rmw_priv_reg(phys_addr_t reg, u32 mask, u32 val); Why these are in the header? Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel