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Wed, 12 Feb 2025 09:44:18 -0800 (PST) Received: from giga-mm.home ([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab7ba97704dsm719671166b.107.2025.02.12.09.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 09:44:18 -0800 (PST) Message-ID: <26ddcdaadd777f170dbab51ab840c899f0edde24.camel@gmail.com> Subject: Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files From: Alexander Sverdlin To: Krzysztof Kozlowski , Inochi Amaoto , soc@lists.linux.dev Cc: Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Chao Wei Date: Wed, 12 Feb 2025 18:44:15 +0100 In-Reply-To: <33654180-5488-4601-9103-8e4218c4a198@kernel.org> References: <20250210220951.1248533-1-alexander.sverdlin@gmail.com> <20250210220951.1248533-2-alexander.sverdlin@gmail.com> <708cdc497b8474609989395dbf8a0898037a22de.camel@gmail.com> <33654180-5488-4601-9103-8e4218c4a198@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250212_094420_567318_16A4A52C X-CRM114-Status: GOOD ( 26.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi=20 On Wed, 2025-02-12 at 17:46 +0100, Krzysztof Kozlowski wrote: > > > > Make the peripheral device tree re-usable on ARM64 platform by movi= ng CPU > > > > core and interrupt controllers' parts into the respective per-SoC .= dtsi > > > > files. > > > >=20 > > > > Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nub= ering > > > > into "plic" interrupt-controller numbering. > > > >=20 > > > > Have a nice refactoring side-effect that "plic" and "clint" "compat= ible" > > > > property is not specified outside of the corresponding device itsel= f. > > > >=20 > > > > Signed-off-by: Alexander Sverdlin > > > > --- > > > > Changelog: > > > > v2: > > > > - instead of carving out peripherals' part, carve out ARCH-specific= s (CPU > > > > core, interrupt controllers) and spread them among 3 SoC .dtsi file= s which > > > > included cv18xx.dtsi; > > > > - define a label for the "soc" node and use it in the newly introdu= ced DTs; > > > >=20 > > > > =C2=A0arch/riscv/boot/dts/sophgo/cv1800b.dtsi=C2=A0=C2=A0=C2=A0 | 6= 4 ++++++++++++--- > > > > =C2=A0arch/riscv/boot/dts/sophgo/cv1812h.dtsi=C2=A0=C2=A0=C2=A0 | 6= 4 ++++++++++++--- > > > > =C2=A0arch/riscv/boot/dts/sophgo/cv181x.dtsi=C2=A0=C2=A0=C2=A0=C2= =A0 |=C2=A0 2 +- > > > > =C2=A0arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 +++++++++++++= + > > > > =C2=A0arch/riscv/boot/dts/sophgo/cv18xx.dtsi=C2=A0=C2=A0=C2=A0=C2= =A0 | 91 ++++++---------------- > > > > =C2=A0arch/riscv/boot/dts/sophgo/sg2002.dtsi=C2=A0=C2=A0=C2=A0=C2= =A0 | 64 ++++++++++++--- > > > > =C2=A06 files changed, 240 insertions(+), 102 deletions(-) > > > > =C2=A0create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi > > > >=20 > > > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/b= oot/dts/sophgo/cv1800b.dtsi > > > > index aa1f5df100f0..eef2884b36f9 100644 > > > > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > > > @@ -3,6 +3,8 @@ > > > > =C2=A0 * Copyright (C) 2023 Jisheng Zhang > > > > =C2=A0 */ > > > > =C2=A0 > > > > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) > > > > + > > > > =C2=A0#include > > > > =C2=A0#include "cv18xx.dtsi" > > > > =C2=A0 > > > > @@ -14,22 +16,62 @@ memory@80000000 { > > > > =C2=A0 reg =3D <0x80000000 0x4000000>; > > > > =C2=A0 }; > > > > =C2=A0 > > >=20 > > > > - soc { > > > > - pinctrl: pinctrl@3001000 { > > > > - compatible =3D "sophgo,cv1800b-pinctrl"; > > > > - reg =3D <0x03001000 0x1000>, > > > > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > > > - reg-names =3D "sys", "rtc"; > > >=20 > > >=20 > > > > + cpus: cpus { > > > > + #address-cells =3D <1>; > > > > + #size-cells =3D <0>; > > > > + timebase-frequency =3D <25000000>; > > > > + > > > > + cpu0: cpu@0 { > > > > + compatible =3D "thead,c906", "riscv"; > > > > + device_type =3D "cpu"; > > > > + reg =3D <0>; > > > > + d-cache-block-size =3D <64>; > > > > + d-cache-sets =3D <512>; > > > > + d-cache-size =3D <65536>; > > > > + i-cache-block-size =3D <64>; > > > > + i-cache-sets =3D <128>; > > > > + i-cache-size =3D <32768>; > > > > + mmu-type =3D "riscv,sv39"; > > > > + riscv,isa =3D "rv64imafdc"; > > > > + riscv,isa-base =3D "rv64i"; > > > > + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr"= , "zicsr", > > > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "zifencei", "zihpm"; > > > > + > > > > + cpu0_intc: interrupt-controller { > > > > + compatible =3D "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + #interrupt-cells =3D <1>; > > > > + }; > > > > =C2=A0 }; > > > > =C2=A0 }; > > > > =C2=A0}; > > >=20 > > > Make all soc definition include the common cpu file.=20 > > > Not just copy it. > >=20 > > I was acting according to Krzysztof's suggestion: > > https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel= .org/ > >=20 > > Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core += interrupt > > controllers into it. Would it make sense? >=20 >=20 > I don't understand the original suggestion. This is the snippet in question: ---[ cut ]--- #define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) / { cpus: cpus { #address-cells =3D <1>; #size-cells =3D <0>; timebase-frequency =3D <25000000>; cpu0: cpu@0 { compatible =3D "thead,c906", "riscv"; device_type =3D "cpu"; reg =3D <0>; d-cache-block-size =3D <64>; d-cache-sets =3D <512>; d-cache-size =3D <65536>; i-cache-block-size =3D <64>; i-cache-sets =3D <128>; i-cache-size =3D <32768>; mmu-type =3D "riscv,sv39"; riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr"= , "zifencei", "zihpm"; cpu0_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; interrupt-controller; #interrupt-cells =3D <1>; }; }; }; }; &soc { interrupt-parent =3D <&plic>; dma-noncoherent; plic: interrupt-controller@70000000 { reg =3D <0x70000000 0x4000000>; interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; interrupt-controller; #address-cells =3D <0>; #interrupt-cells =3D <2>; riscv,ndev =3D <101>; }; clint: timer@74000000 { reg =3D <0x74000000 0x10000>; interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; }; }; ---[ cut ]--- Inochi's proposal is to put it into separate cv18xx-cpu-intc.dtsi and include the latter in 3 other SoC-specific .dtsis. In v2 I've just duplicated the above snippet 3 times (refer to diffstat above). What are your thoughts? In Renesas everything is duplicated, I believe. Sophgo outsources much smaller snippets into .dtsi (refer to cv181x.dtsi).= =20 > Inochi, please trim unnecessary context from replies. --=20 Alexander Sverdlin.