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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id g3-20020a170906c18300b00a3ed811cff9sm3404825ejz.154.2024.02.22.10.26.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Feb 2024 10:26:10 -0800 (PST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Vasily Khoruzhick , Yangtao Li , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Martin Botka , Maksim Kiselev , Bob McChesney , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH v5 1/7] soc: sunxi: sram: export register 0 for THS on H616 Date: Thu, 22 Feb 2024 19:26:08 +0100 Message-ID: <2717467.mvXUDI8C0e@jernej-laptop> In-Reply-To: <20240219153639.179814-2-andre.przywara@arm.com> References: <20240219153639.179814-1-andre.przywara@arm.com> <20240219153639.179814-2-andre.przywara@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240222_102613_923263_78CE95F8 X-CRM114-Status: GOOD ( 29.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dne ponedeljek, 19. februar 2024 ob 16:36:33 CET je Andre Przywara napisal(a): > The Allwinner H616 SoC contains a mysterious bit at register offset 0x0 > in the SRAM control block. If bit 16 is set (the reset value), the > temperature readings of the THS are way off, leading to reports about > 200C, at normal ambient temperatures. Clearing this bits brings the > reported values down to the expected values. > The BSP code clears this bit in firmware (U-Boot), and has an explicit > comment about this, but offers no real explanation. > > Experiments in U-Boot show that register 0x0 has no effect on the SRAM C > visibility: all tested bit settings still allow full read and write > access by the CPU to the whole of SRAM C. Only bit 24 of the register at > offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling > the THS switch functionality as an SRAM region would not reflect reality. > > Since we should not rely on firmware settings, allow other code (the THS > driver) to access this register, by exporting it through the already > existing regmap. This mimics what we already do for the LDO control and > the EMAC register. > > To avoid concurrent accesses to the same register at the same time, by > the SRAM switch code and the regmap code, use the same lock to protect > the access. The regmap subsystem allows to use an existing lock, so we > just need to hook in there. > > Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec I guess this one goes through sunxi tree, right? Best regards, Jernej > --- > drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c > index 4458b2e0562b0..6eb6cf06278e6 100644 > --- a/drivers/soc/sunxi/sunxi_sram.c > +++ b/drivers/soc/sunxi/sunxi_sram.c > @@ -287,6 +287,7 @@ EXPORT_SYMBOL(sunxi_sram_release); > struct sunxi_sramc_variant { > int num_emac_clocks; > bool has_ldo_ctrl; > + bool has_ths_offset; > }; > > static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = { > @@ -308,8 +309,10 @@ static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = { > > static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = { > .num_emac_clocks = 2, > + .has_ths_offset = true, > }; > > +#define SUNXI_SRAM_THS_OFFSET_REG 0x0 > #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 > #define SUNXI_SYS_LDO_CTRL_REG 0x150 > > @@ -318,6 +321,8 @@ static bool sunxi_sram_regmap_accessible_reg(struct device *dev, > { > const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev); > > + if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset) > + return true; > if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG && > reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4) > return true; > @@ -327,6 +332,20 @@ static bool sunxi_sram_regmap_accessible_reg(struct device *dev, > return false; > } > > +static void sunxi_sram_lock(void *_lock) > +{ > + spinlock_t *lock = _lock; > + > + spin_lock(lock); > +} > + > +static void sunxi_sram_unlock(void *_lock) > +{ > + spinlock_t *lock = _lock; > + > + spin_unlock(lock); > +} > + > static struct regmap_config sunxi_sram_regmap_config = { > .reg_bits = 32, > .val_bits = 32, > @@ -336,6 +355,9 @@ static struct regmap_config sunxi_sram_regmap_config = { > /* other devices have no business accessing other registers */ > .readable_reg = sunxi_sram_regmap_accessible_reg, > .writeable_reg = sunxi_sram_regmap_accessible_reg, > + .lock = sunxi_sram_lock, > + .unlock = sunxi_sram_unlock, > + .lock_arg = &sram_lock, > }; > > static int __init sunxi_sram_probe(struct platform_device *pdev) > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel