[PATCH 36/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-orangepi-cm5-base

Cristian Ciocaltea
2026-04-17T09:27:59Z

The board exposes the GPIO4_B5 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.

Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
index 06120b2db690..a7b47670195c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
@@ -147,6 +147,7 @@ &hdmi0 {
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda
&hdmi_frl_pin>;
+ frl-enable-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
status = "okay";
};

@@ -246,7 +247,7 @@ key1_pin: key1-pin {

hdmi {
hdmi_frl_pin: hdmi-frl-pin {
- rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};

--
2.53.0