From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1CE5C98304 for ; Thu, 24 Sep 2026 04:46:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7oUP9+/Uh7C3DwjAwoA/EBqC2sYE38Fw94Zvzy3z0Sw=; b=l36z1mkc1p0cI60q5HVfLZKta9 Kt7bN0dEEvsVdNWyqNMyoAT4FdnbvQ9zFEyhWqvTL4oDG0iGbqr1iwSr0ooqLm6uUdfbtKHqiXVX2 Ix3SG0VzCggKjQCW7Ks2gNjuTDuCgePkLqSFkql6DsZUqmODRIAxNSGEydrTbL6wuYgdYAUKIBO5p TMTW71dazxWO54KIwFtwOXkgeeloF7rva4p8ZdYLEYv/Hn8HjUcfosb6ZOHKjXHdRECDHpvYK0VD+ bLLdG4c2eYppOxfq1YDxaMyG99kU36bG0WEqGm4uLtv/ToSEA9q9sy4vy+/UyvnUbjJ+MxyV+icH3 5YkGaOTA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1x9bLY-0000000A1UM-1vkJ; Thu, 24 Sep 2026 04:46:12 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1x9bLV-0000000A1U0-13eb for linux-arm-kernel@lists.infradead.org; Thu, 24 Sep 2026 04:46:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 20843143D; Wed, 23 Sep 2026 21:46:02 -0700 (PDT) Received: from [10.164.19.30] (unknown [10.164.19.30]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5E3643F86C; Wed, 23 Sep 2026 21:46:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790225165; bh=twJdAsaPAodbcF/MI4mhg53E/bpYg9gpDeHwjpTU600=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ZsnSmBfszOm6qzkEvFPgQjQ0kQZ5rsw/V9DHea66UnB7W7VSv5h9Ddq4TabOy99Wh XMueywuU9wOiu50kH2brG1fCB0yg3HCNcInkPkgPSEf8VkYfVkp1Wa3Zv1icE/xGNZ zE0kADTabnlTDAY+7Dmq3XLFBQ9ZCA3SmxNMKe9Y= Message-ID: <27fbf794-6fbb-44e3-91e7-d2ae86aae9af@arm.com> Date: Thu, 24 Sep 2026 10:15:59 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: mm: Fix the break-before-make flush range for erratum 2645198 To: Andrea Parri , Catalin Marinas , Will Deacon Cc: Mark Rutland , Ryan Roberts , Ard Biesheuvel , Kevin Brodsky , Anshuman Khandual , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20260923143636.89480-1-parri.andrea@gmail.com> Content-Language: en-US From: Dev Jain In-Reply-To: <20260923143636.89480-1-parri.andrea@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260923_214609_366938_D5B23114 X-CRM114-Status: GOOD ( 19.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 23/09/26 8:06 pm, Andrea Parri wrote: > modify_prot_start_ptes() performs the break-before-make TLB invalidation > required by erratum 2645198 with __flush_tlb_range(), whose third > argument is the end address of the range. It passes nr * PAGE_SIZE > instead of addr + nr * PAGE_SIZE, so __do_flush_tlb_range() computes the > page count as (nr * PAGE_SIZE - addr) >> PAGE_SHIFT. > > For addr > nr * PAGE_SIZE that subtraction underflows, the page count > exceeds the batching limit and the flush degenerates to flush_tlb_mm(), > so a single-page mprotect broadcasts an ASID-wide invalidation and a > full-range mmu notifier call. > > For addr <= nr * PAGE_SIZE only [addr, nr * PAGE_SIZE) is invalidated, > and when the cleared batch starts below nr * PAGE_SIZE the tail is left > in the TLB. The workaround then no longer covers the whole batch, and > for addr == nr * PAGE_SIZE the flush is empty. > > On affected Cortex-A715 CPUs, this can corrupt ESR_ELx and FAR_ELx on the > next instruction abort caused by a permission fault. > > Pass addr + nr * PAGE_SIZE as the end address. > > Fixes: 7efa1cd5f89b5 ("arm64: add batched versions of ptep_modify_prot_start/commit") > Cc: stable@vger.kernel.org > Assisted-by: LLM > Signed-off-by: Andrea Parri > --- Thanks, such typos should be filtered out by LLMs nowadays : ) Reviewed-by: Dev Jain > arch/arm64/mm/mmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c > index 79d90226fd5dc..d4384131e10d8 100644 > --- a/arch/arm64/mm/mmu.c > +++ b/arch/arm64/mm/mmu.c > @@ -2295,7 +2295,7 @@ pte_t modify_prot_start_ptes(struct vm_area_struct *vma, unsigned long addr, > * in cases where cpu is affected with errata #2645198. > */ > if (pte_accessible(vma->vm_mm, pte) && pte_user_exec(pte)) > - __flush_tlb_range(vma, addr, nr * PAGE_SIZE, > + __flush_tlb_range(vma, addr, addr + nr * PAGE_SIZE, > PAGE_SIZE, 3, TLBF_NOWALKCACHE); > } >