[pm-core][PATCH v3 00/21] OMAP4: PM: suspend, CPU-hotplug and CPUilde support

[pm-core][PATCH v3 00/21] OMAP4: PM: suspend, CPU-hotplug and CPUilde support

[Santosh Shilimkar]

V3 updates:
It's same as V2 with couple of minor updates and its rebased on Kevin's
latest pm-core branch.
- Dropped 'enable_off_mode' flag altogether for OMAP4 as discussed on the list.
- Removed non-supported pm debug entries

The following changes since commit 61cbb3172176b84c106bf0f4c32317c472932ab5:
  Kevin Hilman (1):
        Merge branch 'for_2.6.40/pm-misc' into pm-reset

are available in the git repository at:

  git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap4_pm_pmcore_v3
 
Dependent patches and integrated barnch against pm-core branch
are also available at below.
 git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap4_pm_pmcore_dep
 git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap4_pm_pmcore_int
  
V2 updates:
Rebased on Kevin's latest pm-core branch and fixes below comments
from Kevin Hilman <khilman@ti.com>. 
- All acronym fixes
- Use WARN_ON() instead of BUG_ON() with graceful exit.
- Export omap4_get_base*() rather than global address pointers
- CPUidle prepare() hook + hotplug notifier to manage C-state dynamically.
- Dropped debugfs way of changing C-state valid flags in favor of above.

This series adds OMAP4 suspend and cpuidle support till MPU subsystem
(MPUSS) off-mode. The suspend on SMP machines uses cpu-hotplug 
infrastructure to take down the non-boot CPUs. We put secondary
CPU(CPU1 in OMAP4) to OFF state via cpu-hotplug.
In cpuidle too, low power states are attempted only when the
CPU1 is put to OFF state via cpu-hotplug because of hardware
constraints.

Timer wakeup from suspend, debug pm counters and enable_off_mode
provisions are supported as well.

Special thanks to Kevin Hilman <khilman@ti.com> for doing detail
off-the list reviews.

The patches are generated against mainline 2.6.38-rc5 and tested with
OMAP4430 SDP and OMAP4 PANDA board. Any OMAP4 board with ES2.X silicon,
below features should work with this series. On ES1.0, these PM 
features are not supported.
	1. CPU hotplug (CPU is put into off-mode)
	2. Suspend (Both CPUs put to off-mode and MPUSS to OFF/RET)
	3. CPUILDE with below C-states.
		C1 - CPU0 ON + CPU1 ON/OFF + MPU ON + CORE ON
		C2 - CPU0 ON + CPU1 OFF + MPU ON + CORE ON
		C3 - CPU0 OFF + CPU1 OFF + MPU CSWR + CORE ON
		C4 - CPU0 OFF + CPU1 OFF + MPU OFF + CORE ON

In OMAP4 mpuss consist of dual Cortex-A9 with per-cpu local timers
GIC(Generic Interrupt Controller), SCU(Snoop Control Unit) and PL310
L2 cache controller and  CPU0/CPU1 LPRM modules.
CPU0, CPU1 and MPUSS have there own power domain and hence multiple
low power state combinations are possible. The CPU10 and CPU1
Close switch Retention(CSWR) isn't supported by hardware.
Based on various studies, measurements, hardware constraints
and recommendations from hardware team, only below low power
modes are supported on OMAP4.
----------------------------------------
CPU0		CPU1		MPUSS
----------------------------------------
ON		ON		ON
OFF		OFF		CSWR
OFF		OFF		OSWR 
OFF		OFF		OFF
-----------------------------------------
Note: CPU0 is the master core and it is the last CPU to go down
and first to wake-up when MPUSS low power states are attempted

OSWR(Open Switch Retention) is not added as part of this series
because it needs some power domain level support which isn't ready
yet.
	http://www.mail-archive.com/linux-omap at vger.kernel.org/msg38667.html

Powerdomain INACTIVE support is also dropped because of its 
inconsistency between OMAP4 and OMAP3.
More information  on this thread -
	http://www.spinics.net/lists/linux-omap/msg45370.html

The cpu-hotplug and suspend works with omap2plus_defconfig. Not to damage
your file system with current omap2plus_defconfig, disable ARCH_OMAP2 so
that V6 and V7 support is not built together with SMP.
To tryout cpuidle, CONFIG_CPU_IDLE needs to be enabled in the build.

CPU-HOTPLUG commands :
	offline : $echo 0 > /sys/devices/system/cpu/cpu1/online
	online : $echo 1 > /sys/devices/system/cpu/cpu1/online

Suspend :$echo mem > /sys/power/state

cpuilde : To trigger cpuidle deeper C-states on OMAP4, CPU1 needs
	to be offlied
	$echo 0 > /sys/devices/system/cpu/cpu1/online

To see PM debug counters,
	$mount -t debugfs debugfs /proc/sys/debug/
	$cat /proc/sys/debug/pm_debug/count

The following changes since commit 61cbb3172176b84c106bf0f4c32317c472932ab5:
  Kevin Hilman (1):
        Merge branch 'for_2.6.40/pm-misc' into pm-reset

are available in the git repository at:

  git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap4_pm_pmcore_v3

Rajendra Nayak (1):
      OMAP4: cpuidle: Basic CPUidle support

Santosh Shilimkar (20):
      OMAP4: PM: Add omap WakeupGen module support
      OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exit
      OMAP4: PM: Export omap4_get_base*() rather than global address pointers
      OMAP4: PM: Add SAR RAM support
      OMAP4: PM: Add CPUX OFF mode support
      OMAP4: PM: Initialise all the clockdomains to supported states
      OMAP4: PM: Program CPU1 to hit OFF when off-lined
      OMAP4: PM: CPU1 wakeup workaround from Low power modes
      OMAP4: PM: Add GIC distributor and interface enable/disable accessory API
      OMAP4: PM: Add GIC save/restore support
      OMAP4: PM: Add WakeupGen save/restore support
      OMAP4: PM: Add L2 cache lowpower support
      OMAP4: suspend: Add MPUSS RET and OFF support
      OMAP4: pm-debug: Add wakeup timer and debug counters
      OMAP4: cpuidle: Add MPUSS RET OFF states
      OMAP4: cpuidle: Switch to gptimer from twd in deeper C-states.
      OMAP4: cpuidle: Add CPU hotplug notifier and prepare() hook.
      OMAP4: Remove un-used do_wfi() macro.
      OMAP4: PM: Set static dependency between MPUSS-EMIF and MPUSS-L3_1
      OMAP4: PM: Avoid omap4_pm_init() on OMAP4430 ES1.0

 arch/arm/mach-omap2/Makefile                      |    8 +-
 arch/arm/mach-omap2/cpuidle44xx.c                 |  352 ++++++++++++++++
 arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |   41 ++
 arch/arm/mach-omap2/include/mach/omap4-common.h   |   73 +++-
 arch/arm/mach-omap2/omap-hotplug.c                |   30 ++-
 arch/arm/mach-omap2/omap-smp.c                    |   32 ++-
 arch/arm/mach-omap2/omap-wakeupgen.c              |  319 +++++++++++++++
 arch/arm/mach-omap2/omap4-common.c                |   86 ++++-
 arch/arm/mach-omap2/omap4-mpuss-lowpower.c        |  451 +++++++++++++++++++++
 arch/arm/mach-omap2/omap4-sar-layout.h            |   66 +++
 arch/arm/mach-omap2/pm-debug.c                    |   11 +-
 arch/arm/mach-omap2/pm.h                          |    1 +
 arch/arm/mach-omap2/pm44xx.c                      |  138 ++++++-
 arch/arm/mach-omap2/sleep44xx.S                   |  404 ++++++++++++++++++
 arch/arm/plat-omap/include/plat/omap44xx.h        |    1 +
 15 files changed, 1980 insertions(+), 33 deletions(-)
 create mode 100644 arch/arm/mach-omap2/cpuidle44xx.c
 create mode 100644 arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
 create mode 100644 arch/arm/mach-omap2/omap-wakeupgen.c
 create mode 100644 arch/arm/mach-omap2/omap4-mpuss-lowpower.c
 create mode 100644 arch/arm/mach-omap2/omap4-sar-layout.h
 create mode 100644 arch/arm/mach-omap2/sleep44xx.S

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

This patch adds OMAP WakeupGen support. The WakeupGen unit is responsible
for generating wakeup event from the incoming interrupts and enable bits.
The WakeupGen is implemented in MPU Always-On power domain. During normal
operation, WakeupGen delivers external interrupts directly to the GIC.
When the CPUx asserts StandbyWFI, indicating it wants to enter lowpower
state, the Standby Controller checks with the WakeupGen unit using the
idlereq/idleack handshake to make sure there is no incoming interrupts.
The GIC and WakeupGen needs to be kept in synchronisation for proper
interrupt functioning.

Hence this patch hooks up the omap WakeupGen mask/unmask along with GIC using
architecture specific hooks.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/Makefile                      |    3 +-
 arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |   40 ++++
 arch/arm/mach-omap2/omap-wakeupgen.c              |  238 +++++++++++++++++++++
 arch/arm/mach-omap2/omap4-common.c                |    3 +
 4 files changed, 283 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
 create mode 100644 arch/arm/mach-omap2/omap-wakeupgen.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 82b2a67..9b654bf 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -24,7 +24,8 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 obj-$(CONFIG_SMP)			+= omap-smp.o omap-headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)		+= timer-mpu.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)		+= omap44xx-smc.o omap4-common.o
+obj-$(CONFIG_ARCH_OMAP4)		+= omap44xx-smc.o omap4-common.o \
+					   omap-wakeupgen.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
new file mode 100644
index 0000000..f10d106
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -0,0 +1,40 @@
+/*
+ * OMAP WakeupGen header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_WAKEUPGEN_H
+#define OMAP_ARCH_WAKEUPGEN_H
+
+#define OMAP_WKG_CONTROL_0			0x00
+#define OMAP_WKG_ENB_A_0			0x10
+#define OMAP_WKG_ENB_B_0			0x14
+#define OMAP_WKG_ENB_C_0			0x18
+#define OMAP_WKG_ENB_D_0			0x1c
+#define OMAP_WKG_ENB_SECURE_A_0			0x20
+#define OMAP_WKG_ENB_SECURE_B_0			0x24
+#define OMAP_WKG_ENB_SECURE_C_0			0x28
+#define OMAP_WKG_ENB_SECURE_D_0			0x2c
+#define OMAP_WKG_ENB_A_1			0x410
+#define OMAP_WKG_ENB_B_1			0x414
+#define OMAP_WKG_ENB_C_1			0x418
+#define OMAP_WKG_ENB_D_1			0x41c
+#define OMAP_WKG_ENB_SECURE_A_1			0x420
+#define OMAP_WKG_ENB_SECURE_B_1			0x424
+#define OMAP_WKG_ENB_SECURE_C_1			0x428
+#define OMAP_WKG_ENB_SECURE_D_1			0x42c
+#define OMAP_AUX_CORE_BOOT_0			0x800
+#define OMAP_AUX_CORE_BOOT_1			0x804
+#define OMAP_PTMSYNCREQ_MASK			0xc00
+#define OMAP_PTMSYNCREQ_EN			0xc04
+#define OMAP_TIMESTAMPCYCLELO			0xc08
+#define OMAP_TIMESTAMPCYCLEHI			0xc0c
+
+extern int __init omap_wakeupgen_init(void);
+extern void omap_wakeupgen_irqmask_all(unsigned int cpu, unsigned int set);
+#endif
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
new file mode 100644
index 0000000..d9d2a3e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -0,0 +1,238 @@
+/*
+ * OMAP WakeupGen Source file
+ *
+ * The WakeupGen unit is responsible for generating wakeup event from the
+ * incoming interrupts and enable bits. The WakeupGen is implemented in MPU
+ * always-On power domain. The WakeupGen consists of two sub-units, one for
+ * each CPU and manages only SPI interrupts. Hardware requirements is that
+ * the GIC and WakeupGen should be kept in sync for proper operation.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include <asm/hardware/gic.h>
+
+#include <mach/omap-wakeupgen.h>
+
+#define NR_BANKS		4
+#define MAX_IRQS		128
+#define WKG_MASK_ALL		0x00000000
+#define WKG_UNMASK_ALL		0xffffffff
+#define CPU_ENA_OFFSET		0x400
+#define CPU0_ID			0x0
+#define CPU1_ID			0x1
+
+/* WakeupGen Base addres */
+static void __iomem *wakeupgen_base;
+static DEFINE_PER_CPU(u32 [NR_BANKS], irqmasks);
+static DEFINE_SPINLOCK(wakeupgen_lock);
+
+/*
+ * Static helper functions
+ */
+
+static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
+{
+	return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
+				(cpu * CPU_ENA_OFFSET) + (idx * 4));
+}
+
+static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
+{
+	__raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
+				(cpu * CPU_ENA_OFFSET) + (idx * 4));
+}
+
+static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
+{
+	u8 i;
+
+	for (i = 0; i < NR_BANKS; i++)
+		wakeupgen_writel(reg, i, cpu);
+}
+
+static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
+{
+	unsigned int spi_irq;
+
+	/*
+	 * PPIs and SGIs are not supported
+	 */
+	if (irq < OMAP44XX_IRQ_GIC_START)
+		return -EINVAL;
+
+	/*
+	 * Subtract the GIC offset
+	 */
+	spi_irq = irq - OMAP44XX_IRQ_GIC_START;
+	if (spi_irq > MAX_IRQS) {
+		pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
+		return -EINVAL;
+	}
+
+	/*
+	 * Each wakeup gen register controls 32
+	 * interrupts. i.e 1 bit per SPI IRQ
+	 */
+	*reg_index = spi_irq >> 5;
+	*bit_posn = spi_irq %= 32;
+
+	return 0;
+}
+
+static void _wakeupgen_clear(unsigned int irq)
+{
+	unsigned int cpu = smp_processor_id();
+	u32 val, bit_number;
+	u8 i;
+
+	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
+		return;
+
+	val = wakeupgen_readl(i, cpu);
+	val &= ~BIT(bit_number);
+	wakeupgen_writel(val, i, cpu);
+}
+
+static void _wakeupgen_set(unsigned int irq)
+{
+	unsigned int cpu = smp_processor_id();
+	u32 val, bit_number;
+	u8 i;
+
+	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
+		return;
+
+	val = wakeupgen_readl(i, cpu);
+	val |= BIT(bit_number);
+	wakeupgen_writel(val, i, cpu);
+}
+
+static void _wakeupgen_save_masks(unsigned int cpu)
+{
+	u8 i;
+
+	for (i = 0; i < NR_BANKS; i++)
+		per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
+}
+
+static void _wakeupgen_restore_masks(unsigned int cpu)
+{
+	u8 i;
+
+	for (i = 0; i < NR_BANKS; i++)
+		wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
+}
+
+/*
+ * Architecture specific Mask extensiom
+ */
+static void wakeupgen_mask(struct irq_data *d)
+{
+	spin_lock(&wakeupgen_lock);
+	_wakeupgen_clear(d->irq);
+	spin_unlock(&wakeupgen_lock);
+}
+
+/*
+ * Architecture specific Unmask extensiom
+ */
+static void wakeupgen_unmask(struct irq_data *d)
+{
+
+	spin_lock(&wakeupgen_lock);
+	_wakeupgen_set(d->irq);
+	spin_unlock(&wakeupgen_lock);
+}
+
+#ifdef CONFIG_PM
+/*
+ * Architecture specific set_wake extension
+ */
+static int wakeupgen_set_wake(struct irq_data *d, unsigned int on)
+{
+	spin_lock(&wakeupgen_lock);
+	if (on)
+		_wakeupgen_set(d->irq);
+	else
+		_wakeupgen_clear(d->irq);
+	spin_unlock(&wakeupgen_lock);
+
+	return 0;
+}
+
+#else
+#define wakeupgen_set_wake	NULL
+#endif
+
+/**
+ * omap_wakeupgen_irqmask_all() -  Mask or unmask interrupts
+ * @cpu - CPU ID
+ * @set - The IRQ register mask.
+ *	0 = Mask all interrupts on the 'cpu'
+ *	1 = Unmask all interrupts on the 'cpu'
+ *
+ * Ensure that the initial mask is maintained. This is faster than
+ * iterating through GIC rgeisters to arrive at the correct masks
+ */
+void omap_wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
+{
+	if (omap_rev() == OMAP4430_REV_ES1_0)
+		return;
+
+	spin_lock(&wakeupgen_lock);
+	if (set) {
+		_wakeupgen_save_masks(cpu);
+		_wakeupgen_set_all(cpu, WKG_MASK_ALL);
+	} else {
+		_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
+		_wakeupgen_restore_masks(cpu);
+	}
+	spin_unlock(&wakeupgen_lock);
+}
+
+/*
+ * Initialse the wakeupgen module
+ */
+int __init omap_wakeupgen_init(void)
+{
+	u8 i;
+
+	/* Not supported on on OMAP4 ES1.0 silicon */
+	if (omap_rev() == OMAP4430_REV_ES1_0) {
+		WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
+		return -EPERM;
+	}
+
+	/* Static mapping, never released */
+	wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
+	if (WARN_ON(!wakeupgen_base))
+		return -ENODEV;
+
+	/* Clear all IRQ bitmasks at wakeupGen level */
+	for (i = 0; i < NR_BANKS; i++) {
+		wakeupgen_writel(0, i, CPU0_ID);
+		wakeupgen_writel(0, i, CPU1_ID);
+	}
+
+	/*
+	 * Override gic architecture specific fucntioms to add
+	 * OMAP WakeupGen interrupt controller along with GIC
+	 */
+	gic_arch_extn.irq_mask = wakeupgen_mask;
+	gic_arch_extn.irq_unmask = wakeupgen_unmask;
+	gic_arch_extn.irq_set_wake = wakeupgen_set_wake;
+
+	return 0;
+}
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 1926864..559d227 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -21,6 +21,7 @@
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
+#include <mach/omap-wakeupgen.h>
 
 #ifdef CONFIG_CACHE_L2X0
 void __iomem *l2cache_base;
@@ -41,6 +42,8 @@ void __init gic_init_irq(void)
 	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
 	BUG_ON(!gic_cpu_base);
 
+	omap_wakeupgen_init();
+
 	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
 }
 
-- 
1.6.0.4

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -21,6 +21,7 @@
>  
>  #include <mach/hardware.h>
>  #include <mach/omap4-common.h>
> +#include <mach/omap-wakeupgen.h>
>  
>  #ifdef CONFIG_CACHE_L2X0
>  void __iomem *l2cache_base;
> @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
>  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
>  	BUG_ON(!gic_cpu_base);
>  
> +	omap_wakeupgen_init();
> +
>  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
>  }

Do you really need to initialize all of this that early?

Tony

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 22:47]:
> > From: Tony Lindgren [mailto:tony at atomide.com]
> >
> > Do you really need to initialize all of this that early?
> >
> Yes. It's a interrupt controller extension and needs to work
> together with GIC.

Hmm to me it seems that the gic_arch_extn functions should be
all NULL during runtime operation, and the wake-up generator
should be programmed only before entering an idle state.

Then the wake-up generator can be cleared after delivering
the wake-up event(s).

Or am I missing something on why this should be enabled all
the time?

BTW, looks like you got few typos in the comments in this
patch, noticed these while reading:

Hardware requirements is
GIC rgeisters
gic architecture specific fucntioms

I know I'm making tons of typos too ;)

Tony

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh]

On 3/29/2011 10:31 PM, Tony Lindgren wrote:
> * Santosh Shilimkar<santosh.shilimkar@ti.com>  [110328 22:47]:
>>> From: Tony Lindgren [mailto:tony at atomide.com]
>>>
>>> Do you really need to initialize all of this that early?
>>>
>> Yes. It's a interrupt controller extension and needs to work
>> together with GIC.
>
> Hmm to me it seems that the gic_arch_extn functions should be
> all NULL during runtime operation, and the wake-up generator
> should be programmed only before entering an idle state.
>
> Then the wake-up generator can be cleared after delivering
> the wake-up event(s).
>
> Or am I missing something on why this should be enabled all
> the time?
>
Yep. The WakeupGen sits between GIC and CPU and can
gate the interrupts in normal operation too. It's
mandatory that the interrupt mask at GIC and WakeupGen
matches to deliver the interrupt to CPU.

This is the reason why all the necessary GIC hooks are
populated with it so that they work together.

So far without this patch all interrupts at WakeupGen
level were always enabled and hence there was no issue.

> BTW, looks like you got few typos in the comments in this
> patch, noticed these while reading:
>
> Hardware requirements is
> GIC rgeisters
> gic architecture specific fucntioms
>
I do lot of them :(
Will fix these typos.

Regards
Santosh

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Tony Lindgren]

* Santosh <santosh.shilimkar@ti.com> [110329 23:13]:
> On 3/29/2011 10:31 PM, Tony Lindgren wrote:
> >* Santosh Shilimkar<santosh.shilimkar@ti.com>  [110328 22:47]:
> >>>From: Tony Lindgren [mailto:tony at atomide.com]
> >>>
> >>>Do you really need to initialize all of this that early?
> >>>
> >>Yes. It's a interrupt controller extension and needs to work
> >>together with GIC.
> >
> >Hmm to me it seems that the gic_arch_extn functions should be
> >all NULL during runtime operation, and the wake-up generator
> >should be programmed only before entering an idle state.
> >
> >Then the wake-up generator can be cleared after delivering
> >the wake-up event(s).
> >
> >Or am I missing something on why this should be enabled all
> >the time?
> >
> Yep. The WakeupGen sits between GIC and CPU and can
> gate the interrupts in normal operation too. It's
> mandatory that the interrupt mask at GIC and WakeupGen
> matches to deliver the interrupt to CPU.

But it seems that the states of GIC and WakeupGen can be
synced up just before hitting an idle mode.

And then the wake-ups only need to be acked after waking
from idle and delivering the interrupts.

> This is the reason why all the necessary GIC hooks are
> populated with it so that they work together.

Hmm I still see no reason to call these functions for every
interrupt during runtime.

AFAIK, these functions only need to be called only once
right after waking from idle.
 
> So far without this patch all interrupts at WakeupGen
> level were always enabled and hence there was no issue.

OK so things work during runtime without calling these
functions for every interrupt. Why then would we want to
call them for each interrupt?

Regards,

Tony

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

On 3/31/2011 12:10 AM, Tony Lindgren wrote:
> * Santosh<santosh.shilimkar@ti.com>  [110329 23:13]:
>> On 3/29/2011 10:31 PM, Tony Lindgren wrote:
>>> * Santosh Shilimkar<santosh.shilimkar@ti.com>   [110328 22:47]:
>>>>> From: Tony Lindgren [mailto:tony at atomide.com]
>>>>>
>>>>> Do you really need to initialize all of this that early?
>>>>>
>>>> Yes. It's a interrupt controller extension and needs to work
>>>> together with GIC.
>>>
>>> Hmm to me it seems that the gic_arch_extn functions should be
>>> all NULL during runtime operation, and the wake-up generator
>>> should be programmed only before entering an idle state.
>>>
>>> Then the wake-up generator can be cleared after delivering
>>> the wake-up event(s).
>>>
>>> Or am I missing something on why this should be enabled all
>>> the time?
>>>
>> Yep. The WakeupGen sits between GIC and CPU and can
>> gate the interrupts in normal operation too. It's
>> mandatory that the interrupt mask at GIC and WakeupGen
>> matches to deliver the interrupt to CPU.
>
> But it seems that the states of GIC and WakeupGen can be
> synced up just before hitting an idle mode.
>
Even during normal operation, WakeUpGen delivers external
interrupts directly to the Interrupt Controller (GIC)
in the CortexA9 MP Core.

> And then the wake-ups only need to be acked after waking
> from idle and delivering the interrupts.
>
>> This is the reason why all the necessary GIC hooks are
>> populated with it so that they work together.
>
> Hmm I still see no reason to call these functions for every
> interrupt during runtime.
>
> AFAIK, these functions only need to be called only once
> right after waking from idle.
>
No. That's pure hack. I think the name of the module
"WakeupGen" seems to be the confusing point.

>> So far without this patch all interrupts at WakeupGen
>> level were always enabled and hence there was no issue.
>
> OK so things work during runtime without calling these
> functions for every interrupt. Why then would we want to
> call them for each interrupt?
>
Because that's the best way to ensure the synchronization
between the GIC and Wakeupgen interrupts mask. The IRQ
framework does this job and we don't have to hack low
level idle code to make special arrangement.

FYI, this is not OMAP4 only problem but even other
architectures based on Cortex-A9 needs an additional
interrupt controller. And they are managed through
the Linux IRQ framework.

As I said earlier it's another interrupt controller
works along with GIC and it's control needs to be
in kernel IRQ framework.

Regards
Santosh

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:20 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen
> module support
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -21,6 +21,7 @@
> >
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > +#include <mach/omap-wakeupgen.h>
> >
> >  #ifdef CONFIG_CACHE_L2X0
> >  void __iomem *l2cache_base;
> > @@ -41,6 +42,8 @@ void __init gic_init_irq(void)
> >  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> >  	BUG_ON(!gic_cpu_base);
> >
> > +	omap_wakeupgen_init();
> > +
> >  	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
> >  }
>
> Do you really need to initialize all of this that early?
>
Yes. It's a interrupt controller extension and needs to work
together with GIC.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Colin Cross]

On Mon, Mar 28, 2011 at 2:22 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
> This patch adds OMAP WakeupGen support. The WakeupGen unit is responsible
> for generating wakeup event from the incoming interrupts and enable bits.
> The WakeupGen is implemented in MPU Always-On power domain. During normal
> operation, WakeupGen delivers external interrupts directly to the GIC.
> When the CPUx asserts StandbyWFI, indicating it wants to enter lowpower
> state, the Standby Controller checks with the WakeupGen unit using the
> idlereq/idleack handshake to make sure there is no incoming interrupts.
> The GIC and WakeupGen needs to be kept in synchronisation for proper
> interrupt functioning.
>
> Hence this patch hooks up the omap WakeupGen mask/unmask along with GIC using
> architecture specific hooks.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Kevin Hilman <khilman@ti.com>

<snip >

> +static void _wakeupgen_clear(unsigned int irq)
> +{
> + ? ? ? unsigned int cpu = smp_processor_id();
> + ? ? ? u32 val, bit_number;
> + ? ? ? u8 i;
> +
> + ? ? ? if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? val = wakeupgen_readl(i, cpu);
> + ? ? ? val &= ~BIT(bit_number);
> + ? ? ? wakeupgen_writel(val, i, cpu);
> +}
> +
> +static void _wakeupgen_set(unsigned int irq)
> +{
> + ? ? ? unsigned int cpu = smp_processor_id();
> + ? ? ? u32 val, bit_number;
> + ? ? ? u8 i;
> +
> + ? ? ? if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? val = wakeupgen_readl(i, cpu);
> + ? ? ? val |= BIT(bit_number);
> + ? ? ? wakeupgen_writel(val, i, cpu);
> +}
Since you already call these from a function that takes a bool as an
argument, using a bool argument here instead of duplicating everything
for set and clear would be simpler.

<snip>

> +/*
> + * Architecture specific Mask extensiom
> + */
> +static void wakeupgen_mask(struct irq_data *d)
> +{
> + ? ? ? spin_lock(&wakeupgen_lock);
> + ? ? ? _wakeupgen_clear(d->irq);
> + ? ? ? spin_unlock(&wakeupgen_lock);
> +}
> +
> +/*
> + * Architecture specific Unmask extensiom
> + */
> +static void wakeupgen_unmask(struct irq_data *d)
> +{
> +
> + ? ? ? spin_lock(&wakeupgen_lock);
> + ? ? ? _wakeupgen_set(d->irq);
> + ? ? ? spin_unlock(&wakeupgen_lock);
> +}
> +
> +#ifdef CONFIG_PM
> +/*
> + * Architecture specific set_wake extension
> + */
> +static int wakeupgen_set_wake(struct irq_data *d, unsigned int on)
> +{
> + ? ? ? spin_lock(&wakeupgen_lock);
> + ? ? ? if (on)
> + ? ? ? ? ? ? ? _wakeupgen_set(d->irq);
> + ? ? ? else
> + ? ? ? ? ? ? ? _wakeupgen_clear(d->irq);
> + ? ? ? spin_unlock(&wakeupgen_lock);
> +
> + ? ? ? return 0;
> +}
> +
> +#else
> +#define wakeupgen_set_wake ? ? NULL
> +#endif

I don't think these are correct, and it probably only works at all due
to lazy disabling of interrupts during suspend.

First, unless I'm missing some code somewhere, all interrupts are
still enabled during suspend.  Any interrupt that has had enable_irq
on it resulted in a call to wakeupgen_unmask, but when disable_irq is
called on all the interrupts during suspend, masking is delayed until
an interrupt is delivered.  If no interrupt is delivered, all enabled
irqs will still be enabled in the wakeupgen module in suspend, and
they will all wake the device out of suspend.

Second, it is possible for a wake interrupt that should be enabled to
end up disabled in suspend.  Consider the following calls that occur
in a driver during its suspend handler:

enable_irq_wake
  ...
  wakeupgen_unmask (irq is now unmasked)
disable_irq (lazy disable, wakeupgen_mask is not called, irq is still unmasked)
<irq occurs>
handle_level_irq
  ...
  wakeupgen_mask (irq is now masked)

The irq will never get unmasked because it is marked disabled, and the
irq will not wake the device from suspend.

wakeupgen_set_wake needs to set or clear bits in memory, and then
those suspend masks need to be copied into the wakeupgen registers
very late in suspend, after interrupts have been disabled at the cpu.
I think syscore_ops is the right place.

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

On 4/2/2011 11:40 AM, Colin Cross wrote:
> On Mon, Mar 28, 2011 at 2:22 AM, Santosh Shilimkar
> <santosh.shilimkar@ti.com>  wrote:
>> This patch adds OMAP WakeupGen support. The WakeupGen unit is responsible
>> for generating wakeup event from the incoming interrupts and enable bits.
>> The WakeupGen is implemented in MPU Always-On power domain. During normal
>> operation, WakeupGen delivers external interrupts directly to the GIC.
>> When the CPUx asserts StandbyWFI, indicating it wants to enter lowpower
>> state, the Standby Controller checks with the WakeupGen unit using the
>> idlereq/idleack handshake to make sure there is no incoming interrupts.
>> The GIC and WakeupGen needs to be kept in synchronisation for proper
>> interrupt functioning.
>>
>> Hence this patch hooks up the omap WakeupGen mask/unmask along with GIC using
>> architecture specific hooks.
>>
>> Signed-off-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
>> Cc: Kevin Hilman<khilman@ti.com>
>
> <snip>
>
>> +static void _wakeupgen_clear(unsigned int irq)
>> +{
>> +       unsigned int cpu = smp_processor_id();
>> +       u32 val, bit_number;
>> +       u8 i;
>> +
>> +       if (_wakeupgen_get_irq_info(irq,&bit_number,&i))
>> +               return;
>> +
>> +       val = wakeupgen_readl(i, cpu);
>> +       val&= ~BIT(bit_number);
>> +       wakeupgen_writel(val, i, cpu);
>> +}
>> +
>> +static void _wakeupgen_set(unsigned int irq)
>> +{
>> +       unsigned int cpu = smp_processor_id();
>> +       u32 val, bit_number;
>> +       u8 i;
>> +
>> +       if (_wakeupgen_get_irq_info(irq,&bit_number,&i))
>> +               return;
>> +
>> +       val = wakeupgen_readl(i, cpu);
>> +       val |= BIT(bit_number);
>> +       wakeupgen_writel(val, i, cpu);
>> +}
> Since you already call these from a function that takes a bool as an
> argument, using a bool argument here instead of duplicating everything
> for set and clear would be simpler.
>
First version of this patch has this done under single function as you
said. Kevin suggested to have separate functions for better readability.

> <snip>
>
>> +/*
>> + * Architecture specific Mask extensiom
>> + */
>> +static void wakeupgen_mask(struct irq_data *d)
>> +{
>> +       spin_lock(&wakeupgen_lock);
>> +       _wakeupgen_clear(d->irq);
>> +       spin_unlock(&wakeupgen_lock);
>> +}
>> +
>> +/*
>> + * Architecture specific Unmask extensiom
>> + */
>> +static void wakeupgen_unmask(struct irq_data *d)
>> +{
>> +
>> +       spin_lock(&wakeupgen_lock);
>> +       _wakeupgen_set(d->irq);
>> +       spin_unlock(&wakeupgen_lock);
>> +}
>> +
>> +#ifdef CONFIG_PM
>> +/*
>> + * Architecture specific set_wake extension
>> + */
>> +static int wakeupgen_set_wake(struct irq_data *d, unsigned int on)
>> +{
>> +       spin_lock(&wakeupgen_lock);
>> +       if (on)
>> +               _wakeupgen_set(d->irq);
>> +       else
>> +               _wakeupgen_clear(d->irq);
>> +       spin_unlock(&wakeupgen_lock);
>> +
>> +       return 0;
>> +}
>> +
>> +#else
>> +#define wakeupgen_set_wake     NULL
>> +#endif
>
> I don't think these are correct, and it probably only works at all due
> to lazy disabling of interrupts during suspend.
>
> First, unless I'm missing some code somewhere, all interrupts are
> still enabled during suspend.  Any interrupt that has had enable_irq
> on it resulted in a call to wakeupgen_unmask, but when disable_irq is
> called on all the interrupts during suspend, masking is delayed until
> an interrupt is delivered.  If no interrupt is delivered, all enabled
> irqs will still be enabled in the wakeupgen module in suspend, and
> they will all wake the device out of suspend.
>
During suspend it's expected that the drivers disables there interrupts
as part of suspend hooks. One can used "set_wake" API's to
enable/disable wakeups from suspend.


> Second, it is possible for a wake interrupt that should be enabled to
> end up disabled in suspend.  Consider the following calls that occur
> in a driver during its suspend handler:
>
> enable_irq_wake
>    ...
>    wakeupgen_unmask (irq is now unmasked)
> disable_irq (lazy disable, wakeupgen_mask is not called, irq is still unmasked)
> <irq occurs>
> handle_level_irq
>    ...
>    wakeupgen_mask (irq is now masked)
>
> The irq will never get unmasked because it is marked disabled, and the
> irq will not wake the device from suspend.
>
> wakeupgen_set_wake needs to set or clear bits in memory, and then
> those suspend masks need to be copied into the wakeupgen registers
> very late in suspend, after interrupts have been disabled at the cpu.
> I think syscore_ops is the right place.
>
This is a good point about lazy disabling. Copy to memory happens
already as part of save in SAR layout.
Will think over this one. Thanks for bringing this point here.

Regards
Santosh

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Colin Cross]

On Sat, Apr 2, 2011 at 2:40 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
> On 4/2/2011 11:40 AM, Colin Cross wrote:
>>
>> On Mon, Mar 28, 2011 at 2:22 AM, Santosh Shilimkar
>> <santosh.shilimkar@ti.com> ?wrote:
>>>
>>> This patch adds OMAP WakeupGen support. The WakeupGen unit is responsible
>>> for generating wakeup event from the incoming interrupts and enable bits.
>>> The WakeupGen is implemented in MPU Always-On power domain. During normal
>>> operation, WakeupGen delivers external interrupts directly to the GIC.
>>> When the CPUx asserts StandbyWFI, indicating it wants to enter lowpower
>>> state, the Standby Controller checks with the WakeupGen unit using the
>>> idlereq/idleack handshake to make sure there is no incoming interrupts.
>>> The GIC and WakeupGen needs to be kept in synchronisation for proper
>>> interrupt functioning.
>>>
>>> Hence this patch hooks up the omap WakeupGen mask/unmask along with GIC
>>> using
>>> architecture specific hooks.
>>>
>>> Signed-off-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
>>> Cc: Kevin Hilman<khilman@ti.com>
>>
>> <snip>
>>
>>> +static void _wakeupgen_clear(unsigned int irq)
>>> +{
>>> + ? ? ? unsigned int cpu = smp_processor_id();
>>> + ? ? ? u32 val, bit_number;
>>> + ? ? ? u8 i;
>>> +
>>> + ? ? ? if (_wakeupgen_get_irq_info(irq,&bit_number,&i))
>>> + ? ? ? ? ? ? ? return;
>>> +
>>> + ? ? ? val = wakeupgen_readl(i, cpu);
>>> + ? ? ? val&= ~BIT(bit_number);
>>> + ? ? ? wakeupgen_writel(val, i, cpu);
>>> +}
>>> +
>>> +static void _wakeupgen_set(unsigned int irq)
>>> +{
>>> + ? ? ? unsigned int cpu = smp_processor_id();
>>> + ? ? ? u32 val, bit_number;
>>> + ? ? ? u8 i;
>>> +
>>> + ? ? ? if (_wakeupgen_get_irq_info(irq,&bit_number,&i))
>>> + ? ? ? ? ? ? ? return;
>>> +
>>> + ? ? ? val = wakeupgen_readl(i, cpu);
>>> + ? ? ? val |= BIT(bit_number);
>>> + ? ? ? wakeupgen_writel(val, i, cpu);
>>> +}
>>
>> Since you already call these from a function that takes a bool as an
>> argument, using a bool argument here instead of duplicating everything
>> for set and clear would be simpler.
>>
> First version of this patch has this done under single function as you
> said. Kevin suggested to have separate functions for better readability.
>
>> <snip>
>>
>>> +/*
>>> + * Architecture specific Mask extensiom
>>> + */
>>> +static void wakeupgen_mask(struct irq_data *d)
>>> +{
>>> + ? ? ? spin_lock(&wakeupgen_lock);
>>> + ? ? ? _wakeupgen_clear(d->irq);
>>> + ? ? ? spin_unlock(&wakeupgen_lock);
>>> +}
>>> +
>>> +/*
>>> + * Architecture specific Unmask extensiom
>>> + */
>>> +static void wakeupgen_unmask(struct irq_data *d)
>>> +{
>>> +
>>> + ? ? ? spin_lock(&wakeupgen_lock);
>>> + ? ? ? _wakeupgen_set(d->irq);
>>> + ? ? ? spin_unlock(&wakeupgen_lock);
>>> +}
>>> +
>>> +#ifdef CONFIG_PM
>>> +/*
>>> + * Architecture specific set_wake extension
>>> + */
>>> +static int wakeupgen_set_wake(struct irq_data *d, unsigned int on)
>>> +{
>>> + ? ? ? spin_lock(&wakeupgen_lock);
>>> + ? ? ? if (on)
>>> + ? ? ? ? ? ? ? _wakeupgen_set(d->irq);
>>> + ? ? ? else
>>> + ? ? ? ? ? ? ? _wakeupgen_clear(d->irq);
>>> + ? ? ? spin_unlock(&wakeupgen_lock);
>>> +
>>> + ? ? ? return 0;
>>> +}
>>> +
>>> +#else
>>> +#define wakeupgen_set_wake ? ? NULL
>>> +#endif
>>
>> I don't think these are correct, and it probably only works at all due
>> to lazy disabling of interrupts during suspend.
>>
>> First, unless I'm missing some code somewhere, all interrupts are
>> still enabled during suspend. ?Any interrupt that has had enable_irq
>> on it resulted in a call to wakeupgen_unmask, but when disable_irq is
>> called on all the interrupts during suspend, masking is delayed until
>> an interrupt is delivered. ?If no interrupt is delivered, all enabled
>> irqs will still be enabled in the wakeupgen module in suspend, and
>> they will all wake the device out of suspend.
>>
> During suspend it's expected that the drivers disables there interrupts
> as part of suspend hooks. One can used "set_wake" API's to
> enable/disable wakeups from suspend.

But because of lazy masking, disabling an interrupt is not the same as
masking.  None of the interrupts will get masked, and they will all
act as wakeup interrupts, even if enable_irq_wake was never called on
it.

>
>> Second, it is possible for a wake interrupt that should be enabled to
>> end up disabled in suspend. ?Consider the following calls that occur
>> in a driver during its suspend handler:
>>
>> enable_irq_wake
>> ? ...
>> ? wakeupgen_unmask (irq is now unmasked)
>> disable_irq (lazy disable, wakeupgen_mask is not called, irq is still
>> unmasked)
>> <irq occurs>
>> handle_level_irq
>> ? ...
>> ? wakeupgen_mask (irq is now masked)
>>
>> The irq will never get unmasked because it is marked disabled, and the
>> irq will not wake the device from suspend.
>>
>> wakeupgen_set_wake needs to set or clear bits in memory, and then
>> those suspend masks need to be copied into the wakeupgen registers
>> very late in suspend, after interrupts have been disabled at the cpu.
>> I think syscore_ops is the right place.
>>
> This is a good point about lazy disabling. Copy to memory happens
> already as part of save in SAR layout.
> Will think over this one. Thanks for bringing this point here.

The key is that mask/unmask and set_wake must act on different mask
data - mask/unmask must take effect immediately, so they must write to
the mask registers, but set_wake takes effect only during suspend, so
it must write to a copy of the mask registers that gets switched in
during suspend.

> Regards
> Santosh
>

[pm-core][PATCH v3 01/21] OMAP4: PM: Add omap WakeupGen module support

[Santosh Shilimkar]

On 4/3/2011 1:17 AM, Colin Cross wrote:
> On Sat, Apr 2, 2011 at 2:40 AM, Santosh Shilimkar
> <santosh.shilimkar@ti.com>  wrote:
>> On 4/2/2011 11:40 AM, Colin Cross wrote:

[....]

>>>> +#ifdef CONFIG_PM
>>>> +/*
>>>> + * Architecture specific set_wake extension
>>>> + */
>>>> +static int wakeupgen_set_wake(struct irq_data *d, unsigned int on)
>>>> +{
>>>> +       spin_lock(&wakeupgen_lock);
>>>> +       if (on)
>>>> +               _wakeupgen_set(d->irq);
>>>> +       else
>>>> +               _wakeupgen_clear(d->irq);
>>>> +       spin_unlock(&wakeupgen_lock);
>>>> +
>>>> +       return 0;
>>>> +}
>>>> +
>>>> +#else
>>>> +#define wakeupgen_set_wake     NULL
>>>> +#endif
>>>
>>> I don't think these are correct, and it probably only works at all due
>>> to lazy disabling of interrupts during suspend.
>>>
>>> First, unless I'm missing some code somewhere, all interrupts are
>>> still enabled during suspend.  Any interrupt that has had enable_irq
>>> on it resulted in a call to wakeupgen_unmask, but when disable_irq is
>>> called on all the interrupts during suspend, masking is delayed until
>>> an interrupt is delivered.  If no interrupt is delivered, all enabled
>>> irqs will still be enabled in the wakeupgen module in suspend, and
>>> they will all wake the device out of suspend.
>>>
>> During suspend it's expected that the drivers disables there interrupts
>> as part of suspend hooks. One can used "set_wake" API's to
>> enable/disable wakeups from suspend.
>
> But because of lazy masking, disabling an interrupt is not the same as
> masking.  None of the interrupts will get masked, and they will all
> act as wakeup interrupts, even if enable_irq_wake was never called on
> it.
>
>>
>>> Second, it is possible for a wake interrupt that should be enabled to
>>> end up disabled in suspend.  Consider the following calls that occur
>>> in a driver during its suspend handler:
>>>
>>> enable_irq_wake
>>>    ...
>>>    wakeupgen_unmask (irq is now unmasked)
>>> disable_irq (lazy disable, wakeupgen_mask is not called, irq is still
>>> unmasked)
>>> <irq occurs>
>>> handle_level_irq
>>>    ...
>>>    wakeupgen_mask (irq is now masked)
>>>
>>> The irq will never get unmasked because it is marked disabled, and the
>>> irq will not wake the device from suspend.
>>>
>>> wakeupgen_set_wake needs to set or clear bits in memory, and then
>>> those suspend masks need to be copied into the wakeupgen registers
>>> very late in suspend, after interrupts have been disabled at the cpu.
>>> I think syscore_ops is the right place.
>>>
>> This is a good point about lazy disabling. Copy to memory happens
>> already as part of save in SAR layout.
>> Will think over this one. Thanks for bringing this point here.
>
> The key is that mask/unmask and set_wake must act on different mask
> data - mask/unmask must take effect immediately, so they must write to
> the mask registers, but set_wake takes effect only during suspend, so
> it must write to a copy of the mask registers that gets switched in
> during suspend.
>
Right. I shall fix the set_wake() API to take care of lazy
disabling of IRQs.

Regards
Santosh

[pm-core][PATCH v3 02/21] OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exit

[Santosh Shilimkar]

OMAP L2X0 and GIC initialisation code uses BUG_ON() for the
ioremap() failure scenarios.

Use WARN_ON() instead and allow graceful function exits.

This was suggsted by Kevin Hilman <khilman@ti.com> during
OMAP4 PM code review.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/omap4-common.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 559d227..8f9b97d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -36,11 +36,13 @@ void __init gic_init_irq(void)
 
 	/* Static mapping, never released */
 	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
-	BUG_ON(!gic_dist_base_addr);
+	if (WARN_ON(!gic_dist_base_addr))
+		return;
 
 	/* Static mapping, never released */
 	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
-	BUG_ON(!gic_cpu_base);
+	if (WARN_ON(!gic_cpu_base))
+		return;
 
 	omap_wakeupgen_init();
 
@@ -68,7 +70,8 @@ static int __init omap_l2_cache_init(void)
 
 	/* Static mapping, never released */
 	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
-	BUG_ON(!l2cache_base);
+	if (WARN_ON(!l2cache_base))
+		return -ENODEV;
 
 	/*
 	 * 16-way associativity, parity disabled
-- 
1.6.0.4

[pm-core][PATCH v3 02/21] OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exit

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:20]:
> OMAP L2X0 and GIC initialisation code uses BUG_ON() for the
> ioremap() failure scenarios.
> 
> Use WARN_ON() instead and allow graceful function exits.
> 
> This was suggsted by Kevin Hilman <khilman@ti.com> during
> OMAP4 PM code review.
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Kevin Hilman <khilman@ti.com>
> ---
>  arch/arm/mach-omap2/omap4-common.c |    9 ++++++---
>  1 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
> index 559d227..8f9b97d 100644
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -36,11 +36,13 @@ void __init gic_init_irq(void)
>  
>  	/* Static mapping, never released */
>  	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
> -	BUG_ON(!gic_dist_base_addr);
> +	if (WARN_ON(!gic_dist_base_addr))
> +		return;
>  
>  	/* Static mapping, never released */
>  	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
> -	BUG_ON(!gic_cpu_base);
> +	if (WARN_ON(!gic_cpu_base))
> +		return;
>  
>  	omap_wakeupgen_init();
>  
> @@ -68,7 +70,8 @@ static int __init omap_l2_cache_init(void)
>  
>  	/* Static mapping, never released */
>  	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> -	BUG_ON(!l2cache_base);
> +	if (WARN_ON(!l2cache_base))
> +		return -ENODEV;
>  
>  	/*
>  	 * 16-way associativity, parity disabled

Hmm to me it seems that if any of these we don't want to
continue.

Tony

[pm-core][PATCH v3 02/21] OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exit

[Santosh Shilimkar]

On 3/29/2011 2:23 AM, Tony Lindgren wrote:
> * Santosh Shilimkar<santosh.shilimkar@ti.com>  [110328 02:20]:
>> OMAP L2X0 and GIC initialisation code uses BUG_ON() for the
>> ioremap() failure scenarios.
>>
>> Use WARN_ON() instead and allow graceful function exits.
>>
>> This was suggsted by Kevin Hilman<khilman@ti.com>  during
>> OMAP4 PM code review.
>>
>> Signed-off-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
>> Cc: Kevin Hilman<khilman@ti.com>
>> ---
>>   arch/arm/mach-omap2/omap4-common.c |    9 ++++++---
>>   1 files changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
>> index 559d227..8f9b97d 100644
>> --- a/arch/arm/mach-omap2/omap4-common.c
>> +++ b/arch/arm/mach-omap2/omap4-common.c
>> @@ -36,11 +36,13 @@ void __init gic_init_irq(void)
>>
>>   	/* Static mapping, never released */
>>   	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
>> -	BUG_ON(!gic_dist_base_addr);
>> +	if (WARN_ON(!gic_dist_base_addr))
>> +		return;
>>
>>   	/* Static mapping, never released */
>>   	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
>> -	BUG_ON(!gic_cpu_base);
>> +	if (WARN_ON(!gic_cpu_base))
>> +		return;
>>
>>   	omap_wakeupgen_init();
>>
>> @@ -68,7 +70,8 @@ static int __init omap_l2_cache_init(void)
>>
>>   	/* Static mapping, never released */
>>   	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
>> -	BUG_ON(!l2cache_base);
>> +	if (WARN_ON(!l2cache_base))
>> +		return -ENODEV;
>>
>>   	/*
>>   	 * 16-way associativity, parity disabled
>
> Hmm to me it seems that if any of these we don't want to
> continue.
>
L2 cache is no problem and kernel can boot without L2 cache
support. I agree with you on interrupt controller init though.

Will drop the interrupt related checks from this patch.

Kevin, Are you ok with it ?

Regards
Santosh

[pm-core][PATCH v3 02/21] OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exit

[Kevin Hilman]

Santosh Shilimkar <santosh.shilimkar@ti.com> writes:

> On 3/29/2011 2:23 AM, Tony Lindgren wrote:
>> * Santosh Shilimkar<santosh.shilimkar@ti.com>  [110328 02:20]:
>>> OMAP L2X0 and GIC initialisation code uses BUG_ON() for the
>>> ioremap() failure scenarios.
>>>
>>> Use WARN_ON() instead and allow graceful function exits.
>>>
>>> This was suggsted by Kevin Hilman<khilman@ti.com>  during
>>> OMAP4 PM code review.
>>>
>>> Signed-off-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
>>> Cc: Kevin Hilman<khilman@ti.com>
>>> ---
>>>   arch/arm/mach-omap2/omap4-common.c |    9 ++++++---
>>>   1 files changed, 6 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
>>> index 559d227..8f9b97d 100644
>>> --- a/arch/arm/mach-omap2/omap4-common.c
>>> +++ b/arch/arm/mach-omap2/omap4-common.c
>>> @@ -36,11 +36,13 @@ void __init gic_init_irq(void)
>>>
>>>   	/* Static mapping, never released */
>>>   	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
>>> -	BUG_ON(!gic_dist_base_addr);
>>> +	if (WARN_ON(!gic_dist_base_addr))
>>> +		return;
>>>
>>>   	/* Static mapping, never released */
>>>   	gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
>>> -	BUG_ON(!gic_cpu_base);
>>> +	if (WARN_ON(!gic_cpu_base))
>>> +		return;
>>>
>>>   	omap_wakeupgen_init();
>>>
>>> @@ -68,7 +70,8 @@ static int __init omap_l2_cache_init(void)
>>>
>>>   	/* Static mapping, never released */
>>>   	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
>>> -	BUG_ON(!l2cache_base);
>>> +	if (WARN_ON(!l2cache_base))
>>> +		return -ENODEV;
>>>
>>>   	/*
>>>   	 * 16-way associativity, parity disabled
>>
>> Hmm to me it seems that if any of these we don't want to
>> continue.
>>
> L2 cache is no problem and kernel can boot without L2 cache
> support. I agree with you on interrupt controller init though.
>
> Will drop the interrupt related checks from this patch.
>
> Kevin, Are you ok with it ?

In general, BUG should only be used when the kernel really can not
possibly continue[1].  I suppose inability to map the GIC falls into
that category.

Kevin


[1] from asm-generic/bug.h:

/*
 * Don't use BUG() or BUG_ON() unless there's really no way out; one
 * example might be detecting data structure corruption in the middle
 * of an operation that can't be backed out of.  If the (sub)system
 * can somehow continue operating, perhaps with reduced functionality,
 * it's probably not BUG-worthy.
 *
 * If you're tempted to BUG(), think again:  is completely giving up
 * really the *only* solution?  There are usually better options, where
 * users don't need to reboot ASAP and can mostly shut down cleanly.
 */

[pm-core][PATCH v3 02/21] OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exit

[Santosh Shilimkar]

On 3/31/2011 7:34 PM, Kevin Hilman wrote:
> Santosh Shilimkar<santosh.shilimkar@ti.com>  writes:
>
>> On 3/29/2011 2:23 AM, Tony Lindgren wrote:
>>> * Santosh Shilimkar<santosh.shilimkar@ti.com>   [110328 02:20]:
>

[...]

>> L2 cache is no problem and kernel can boot without L2 cache
>> support. I agree with you on interrupt controller init though.
>>
>> Will drop the interrupt related checks from this patch.
>>
>> Kevin, Are you ok with it ?
>
> In general, BUG should only be used when the kernel really can not
> possibly continue[1].  I suppose inability to map the GIC falls into
> that category.
>
Thanks. Will drop GIC ones.

Regards
Santosh

[pm-core][PATCH v3 03/21] OMAP4: PM: Export omap4_get_base*() rather than global address pointers

[Santosh Shilimkar]

This patch exports APIs to get base address for GIC
distributor, CPU interface, SCU and PL310 L2 Cache which
are used in OMAP4 PM code.

This was suggested by Kevin Hilman <khilman@ti.com> during
OMAP4 PM code review.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/include/mach/omap4-common.h |   13 +++++++++++--
 arch/arm/mach-omap2/omap-smp.c                  |    6 ++++++
 arch/arm/mach-omap2/omap4-common.c              |   21 ++++++++++++++++++---
 3 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index de441c0..106edef 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -25,11 +25,20 @@
 #endif
 
 #ifdef CONFIG_CACHE_L2X0
-extern void __iomem *l2cache_base;
+extern void __iomem *omap4_get_l2cache_base(void);
 #endif
 
-extern void __iomem *gic_dist_base_addr;
+#ifdef CONFIG_SMP
+extern void __iomem *omap4_get_scu_base(void);
+#else
+static inline void __iomem *omap4_get_scu_base(void)
+{
+	return NULL;
+}
+#endif
 
+extern void __iomem *omap4_get_gic_dist_base(void);
+extern void __iomem *omap4_get_gic_cpu_base(void);
 extern void __init gic_init_irq(void);
 extern void omap_smc1(u32 fn, u32 arg);
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index b66cfe8..4fcaa4a 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -30,6 +30,12 @@ static void __iomem *scu_base;
 
 static DEFINE_SPINLOCK(boot_lock);
 
+
+void __iomem *omap4_get_scu_base(void)
+{
+	return scu_base;
+}
+
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	/*
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 8f9b97d..fdacb9e 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -24,15 +24,25 @@
 #include <mach/omap-wakeupgen.h>
 
 #ifdef CONFIG_CACHE_L2X0
-void __iomem *l2cache_base;
+static void __iomem *l2cache_base;
 #endif
 
-void __iomem *gic_dist_base_addr;
+static void __iomem *gic_dist_base_addr;
+static void __iomem *gic_cpu_base;
 
 
+void __iomem *omap4_get_gic_dist_base(void)
+{
+	return gic_dist_base_addr;
+}
+
+void __iomem *omap4_get_gic_cpu_base(void)
+{
+	return gic_cpu_base;
+}
+
 void __init gic_init_irq(void)
 {
-	void __iomem *gic_cpu_base;
 
 	/* Static mapping, never released */
 	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
@@ -51,6 +61,11 @@ void __init gic_init_irq(void)
 
 #ifdef CONFIG_CACHE_L2X0
 
+void __iomem *omap4_get_l2cache_base(void)
+{
+	return l2cache_base;
+}
+
 static void omap4_l2x0_disable(void)
 {
 	/* Disable PL310 L2 Cache controller */
-- 
1.6.0.4

[pm-core][PATCH v3 04/21] OMAP4: PM: Add SAR RAM support

[Santosh Shilimkar]

This patch adds SAR RAM support on OMAP4430. SAR RAM used to save
and restore the HW context in low power modes.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/include/mach/omap4-common.h |    1 +
 arch/arm/mach-omap2/omap4-common.c              |   31 ++++++++++++++++++++++-
 arch/arm/mach-omap2/omap4-sar-layout.h          |   22 ++++++++++++++++
 arch/arm/plat-omap/include/plat/omap44xx.h      |    1 +
 4 files changed, 54 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/omap4-sar-layout.h

diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 106edef..284180c 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -39,6 +39,7 @@ static inline void __iomem *omap4_get_scu_base(void)
 
 extern void __iomem *omap4_get_gic_dist_base(void);
 extern void __iomem *omap4_get_gic_cpu_base(void);
+extern void __iomem *omap4_get_sar_ram_base(void);
 extern void __init gic_init_irq(void);
 extern void omap_smc1(u32 fn, u32 arg);
 
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index fdacb9e..97d7d8a 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -23,13 +23,15 @@
 #include <mach/omap4-common.h>
 #include <mach/omap-wakeupgen.h>
 
+#include "omap4-sar-layout.h"
+
 #ifdef CONFIG_CACHE_L2X0
 static void __iomem *l2cache_base;
 #endif
 
 static void __iomem *gic_dist_base_addr;
 static void __iomem *gic_cpu_base;
-
+static void __iomem *sar_ram_base;
 
 void __iomem *omap4_get_gic_dist_base(void)
 {
@@ -125,3 +127,30 @@ static int __init omap_l2_cache_init(void)
 }
 early_initcall(omap_l2_cache_init);
 #endif
+
+void __iomem *omap4_get_sar_ram_base(void)
+{
+	return sar_ram_base;
+}
+
+/*
+ * SAR RAM used to save and restore the HW
+ * context in low power modes
+ */
+static int __init omap4_sar_ram_init(void)
+{
+	/*
+	 * To avoid code running on other OMAPs in
+	 * multi-omap builds
+	 */
+	if (!cpu_is_omap44xx())
+		return -ENODEV;
+
+	/* Static mapping, never released */
+	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_8K);
+	if (WARN_ON(!sar_ram_base))
+		return -ENODEV;
+
+	return 0;
+}
+early_initcall(omap4_sar_ram_init);
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
new file mode 100644
index 0000000..1cfb4dd
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -0,0 +1,22 @@
+/*
+ * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+
+/*
+ * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ */
+#define SAR_BANK1_OFFSET		0x0000
+#define SAR_BANK2_OFFSET		0x1000
+#define SAR_BANK3_OFFSET		0x2000
+#define SAR_BANK4_OFFSET		0x3000
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index ea2b8a6..c0d478e 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -45,6 +45,7 @@
 #define OMAP44XX_WKUPGEN_BASE		0x48281000
 #define OMAP44XX_MCPDM_BASE		0x40132000
 #define OMAP44XX_MCPDM_L3_BASE		0x49032000
+#define OMAP44XX_SAR_RAM_BASE		0x4a326000
 
 #define OMAP44XX_MAILBOX_BASE		(L4_44XX_BASE + 0xF4000)
 #define OMAP44XX_HSUSB_OTG_BASE		(L4_44XX_BASE + 0xAB000)
-- 
1.6.0.4

[pm-core][PATCH v3 05/21] OMAP4: PM: Add CPUX OFF mode support

[Santosh Shilimkar]

This patch adds the CPU0 and CPU1 off mode support. CPUX close switch
retention (CSWR) is not supported by hardware design.

The CPUx OFF mode isn't supported on OMAP4430 ES1.0

CPUx sleep code is common for hotplug, suspend and CPUilde.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/Makefile                    |    4 +-
 arch/arm/mach-omap2/include/mach/omap4-common.h |   46 +++
 arch/arm/mach-omap2/omap4-mpuss-lowpower.c      |  240 ++++++++++++++++
 arch/arm/mach-omap2/omap4-sar-layout.h          |   11 +
 arch/arm/mach-omap2/pm44xx.c                    |    6 +
 arch/arm/mach-omap2/sleep44xx.S                 |  339 +++++++++++++++++++++++
 6 files changed, 645 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/omap4-mpuss-lowpower.c
 create mode 100644 arch/arm/mach-omap2/sleep44xx.S

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9b654bf..8558215 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -63,13 +63,15 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o pm_bus.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o \
 					   cpuidle34xx.o pm_bus.o
-obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o \
+					   omap4-mpuss-lowpower.o sleep44xx.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
 
 AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
 AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a
+AFLAGS_sleep44xx.o			:=-Wa,-march=armv7-a
 
 ifeq ($(CONFIG_PM_VERBOSE),y)
 CFLAGS_pm_bus.o				+= -DDEBUG
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 284180c..a6ce905 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -13,6 +13,9 @@
 #ifndef OMAP_ARCH_OMAP4_COMMON_H
 #define OMAP_ARCH_OMAP4_COMMON_H
 
+#include <asm/proc-fns.h>
+
+#ifndef __ASSEMBLER__
 /*
  * wfi used in low power code. Directly opcode is used instead
  * of instruction to avoid mulit-omap build break
@@ -43,4 +46,47 @@ extern void __iomem *omap4_get_sar_ram_base(void);
 extern void __init gic_init_irq(void);
 extern void omap_smc1(u32 fn, u32 arg);
 
+/*
+ * Read MPIDR: Multiprocessor affinity register
+ */
+static inline unsigned int hard_smp_processor_id(void)
+{
+	unsigned int cpunum;
+
+	asm volatile (
+	"mrc	 p15, 0, %0, c0, c0, 5\n"
+		: "=r" (cpunum));
+	return cpunum &= 0x0f;
+}
+
+#if defined(CONFIG_SMP)	&& defined(CONFIG_PM)
+extern int omap4_mpuss_init(void);
+extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
+extern void omap4_cpu_suspend(unsigned int cpu, unsigned int save_state);
+extern void omap4_cpu_resume(void);
+
+#else
+
+static inline int omap4_enter_lowpower(unsigned int cpu,
+					unsigned int power_state)
+{
+	cpu_do_idle();
+	return 0;
+}
+
+static inline int omap4_mpuss_init(void)
+{
+	return 0;
+}
+
+static inline void omap4_cpu_suspend(unsigned int cpu, unsigned int save_state)
+{
+}
+
+static inline void omap4_cpu_resume(void)
+{
+}
+
 #endif
+#endif /* __ASSEMBLER__ */
+#endif /* OMAP_ARCH_OMAP4_COMMON_H */
diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
new file mode 100644
index 0000000..21c5ad3
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
@@ -0,0 +1,240 @@
+/*
+ * OMAP4 MPUSS low power code
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
+ * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
+ * CPU0 and CPU1 LPRM modules.
+ * CPU0, CPU1 and MPUSS each have there own power domain and
+ * hence multiple low power combinations of MPUSS are possible.
+ *
+ * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
+ * because the mode is not supported by hw constraints of dormant
+ * mode. While waking up from the dormant mode, a reset  signal
+ * to the Cortex-A9 processor must be asserted by the external
+ * power controller.
+ *
+ * With architectural inputs and hardware recommendations, only
+ * below modes are supported from power gain vs latency point of view.
+ *
+ *	CPU0		CPU1		MPUSS
+ *	----------------------------------------------
+ *	ON		ON		ON
+ *	ON(Inactive)	OFF		ON(Inactive)
+ *	OFF		OFF		CSWR
+ *	OFF		OFF		OSWR (*TBD)
+ *	OFF		OFF		OFF* (*TBD)
+ *	----------------------------------------------
+ *
+ * Note: CPU0 is the master core and it is the last CPU to go down
+ * and first to wake-up when MPUSS low power states are excercised
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/linkage.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/smp_scu.h>
+#include <asm/system.h>
+
+#include <plat/omap44xx.h>
+#include <mach/omap4-common.h>
+
+#include "omap4-sar-layout.h"
+#include "pm.h"
+#include "powerdomain.h"
+
+#ifdef CONFIG_SMP
+
+struct omap4_cpu_pm_info {
+	struct powerdomain *pwrdm;
+	void __iomem *scu_sar_addr;
+};
+
+static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
+
+/*
+ * Set the CPUx powerdomain's previous power state
+ */
+static inline void set_cpu_next_pwrst(unsigned int cpu_id,
+				unsigned int power_state)
+{
+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+
+	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
+}
+
+/*
+ * Read CPU's previous power state
+ */
+static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
+{
+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+
+	return pwrdm_read_prev_pwrst(pm_info->pwrdm);
+}
+
+/*
+ * Clear the CPUx powerdomain's previous power state
+ */
+static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
+{
+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+
+	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+}
+
+/*
+ * Store the SCU power status value to scratchpad memory
+ */
+static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
+{
+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+	u32 scu_pwr_st;
+
+	switch (cpu_state) {
+	case PWRDM_POWER_RET:
+		scu_pwr_st = SCU_PM_DORMANT;
+		break;
+	case PWRDM_POWER_OFF:
+		scu_pwr_st = SCU_PM_POWEROFF;
+		break;
+	case PWRDM_POWER_ON:
+	case PWRDM_POWER_INACTIVE:
+	default:
+		scu_pwr_st = SCU_PM_NORMAL;
+		break;
+	}
+
+	__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
+}
+
+/*
+ * OMAP4 MPUSS Low Power Entry Function
+ *
+ * The purpose of this function is to manage low power programming
+ * of OMAP4 MPUSS subsystem
+ * Paramenters:
+ *	cpu : CPU ID
+ *	power_state: Targetted Low power state.
+ */
+int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
+{
+	unsigned int save_state = 0;
+	unsigned int wakeup_cpu = hard_smp_processor_id();
+
+	if ((cpu >= NR_CPUS) || (omap_rev() == OMAP4430_REV_ES1_0))
+		goto ret;
+
+	switch (power_state) {
+	case PWRDM_POWER_ON:
+	case PWRDM_POWER_INACTIVE:
+		save_state = 0;
+		break;
+	case PWRDM_POWER_OFF:
+		save_state = 1;
+		break;
+	case PWRDM_POWER_RET:
+	default:
+		/*
+		 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
+		 * doesn't make much scense, since logic is lost and $L1
+		 * needs to be cleaned because of coherency. This makes
+		 * CPUx OSWR equivalent to CPUX OFF and hence not supported
+		 */
+		WARN_ON(1);
+		goto ret;
+	}
+
+	clear_cpu_prev_pwrst(cpu);
+	set_cpu_next_pwrst(cpu, power_state);
+	scu_pwrst_prepare(cpu, power_state);
+
+	/*
+	 * Call low level function  with targeted CPU id
+	 * and its low power state.
+	 */
+	omap4_cpu_suspend(cpu, save_state);
+
+	/*
+	 * Restore the CPUx power state to ON otherwise CPUx
+	 * power domain can transitions to programmed low power
+	 * state while doing WFI outside the low powe code. On
+	 * secure devices, CPUx does WFI which can result in
+	 * domain transition
+	 */
+	wakeup_cpu = hard_smp_processor_id();
+	set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
+
+ret:
+	return 0;
+}
+
+/*
+ * Initialise OMAP4 MPUSS
+ */
+int __init omap4_mpuss_init(void)
+{
+	struct omap4_cpu_pm_info *pm_info;
+	void __iomem *sar_ram_base = omap4_get_sar_ram_base();
+
+	if (omap_rev() == OMAP4430_REV_ES1_0) {
+		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+		return -ENODEV;
+	}
+
+	/* Initilaise per CPU PM information */
+	pm_info = &per_cpu(omap4_pm_info, 0x0);
+	pm_info->scu_sar_addr = sar_ram_base + SCU_OFFSET0;
+	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
+	if (!pm_info->pwrdm) {
+		pr_err("Lookup failed for CPU0 pwrdm\n");
+		return -ENODEV;
+	}
+
+	/* Clear CPU previous power domain state */
+	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+
+	/* Initialise CPU0 power domain state to ON */
+	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+
+	pm_info = &per_cpu(omap4_pm_info, 0x1);
+	pm_info->scu_sar_addr = sar_ram_base + SCU_OFFSET1;
+	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
+	if (!pm_info->pwrdm) {
+		pr_err("Lookup failed for CPU1 pwrdm\n");
+		return -ENODEV;
+	}
+
+	/* Clear CPU previous power domain state */
+	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+
+	/* Initialise CPU1 power domain state to ON */
+	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+
+	/*
+	 * Program the wakeup routine address for the CPU0 and CPU1
+	 * used for OFF or DORMANT wakeup. Wakeup routine address
+	 * is fixed so programit in init itself.
+	 */
+	__raw_writel(virt_to_phys(omap4_cpu_resume),
+			sar_ram_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
+	__raw_writel(virt_to_phys(omap4_cpu_resume),
+			sar_ram_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET);
+
+	return 0;
+}
+
+#endif
+
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index 1cfb4dd..8b71b1e 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -19,4 +19,15 @@
 #define SAR_BANK3_OFFSET		0x2000
 #define SAR_BANK4_OFFSET		0x3000
 
+/* Scratch pad memory offsets from SAR_BANK1 */
+#define CPU0_SAVE_OFFSET			0xb00
+#define CPU1_SAVE_OFFSET			0xc00
+#define MMU_OFFSET				0xd00
+#define SCU_OFFSET0				0xd20
+#define SCU_OFFSET1				0xd24
+
+/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
+#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET		0xa04
+#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET		0xa08
+
 #endif
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 59a870b..5b631f5 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -111,6 +111,12 @@ static int __init omap4_pm_init(void)
 		goto err2;
 	}
 
+	ret = omap4_mpuss_init();
+	if (ret) {
+		pr_err("Failed to initialise OMAP4 MPUSS\n");
+		goto err2;
+	}
+
 #ifdef CONFIG_SUSPEND
 	suspend_set_ops(&omap_pm_ops);
 #endif /* CONFIG_SUSPEND */
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
new file mode 100644
index 0000000..ccaf0e6
--- /dev/null
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -0,0 +1,339 @@
+/*
+ * OMAP44xx CPU low power powerdown and powerup code.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/smp_scu.h>
+#include <asm/memory.h>
+
+#include <plat/omap44xx.h>
+#include <mach/omap4-common.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include "omap4-sar-layout.h"
+
+#ifdef CONFIG_SMP
+
+/* Masks used for MMU manipulation */
+#define TTRBIT_MASK				0xffffc000
+#define TABLE_INDEX_MASK			0xfff00000
+#define TABLE_ENTRY				0x00000c02
+#define CACHE_DISABLE_MASK			0xffffe7fb
+#define TABLE_ADDRESS_OFFSET			0x04
+#define CR_VALUE_OFFSET				0x08
+
+/*
+ * =============================
+ * == CPU suspend entry point ==
+ * =============================
+ *
+ * void omap4_cpu_suspend(unsigned int cpu, unsigned int save_state)
+ *
+ * This function code saves the CPU context and performs the CPU
+ * power down sequence. Calling WFI effectively changes the CPU
+ * power domains states to the desired target power state.
+ *
+ * @cpu : contains cpu id (r0)
+ * @save_state : contains context save state (r1)
+ *	0 - No context lost
+ * 	1 - CPUx L1 and logic lost: MPUSS CSWR
+ * 	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
+ *	3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
+ * @return: This function never returns for CPU OFF and DORMANT power states.
+ * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
+ * from this follows a full CPU reset path via ROM code to CPU restore code.
+ * It returns to the caller for CPU INACTIVE and ON power states or in case
+ * CPU failed to transition to targeted OFF/DORMANT state.
+ */
+
+ENTRY(omap4_cpu_suspend)
+	stmfd	sp!, {r0-r12, lr}		@ Save registers on stack
+	cmp	r1, #0x0
+	beq	do_WFI				@ Nothing to save, jump to WFI
+	mov	r5, r0
+	bl	omap4_get_sar_ram_base
+	mov	r8, r0
+	ands	r5, r5, #0x0f
+	orreq	r8, r8, #CPU0_SAVE_OFFSET
+	orrne	r8, r8, #CPU1_SAVE_OFFSET
+
+	/*
+	 * Save only needed CPU CP15 registers. VFP, breakpoint,
+	 * performance monitor registers are not saved. Generic
+	 * code suppose to take care of those.
+	 */
+	mov	r4, sp				@ Store sp
+	mrs	r5, spsr			@ Store spsr
+	mov	r6, lr				@ Store lr
+	stmia	r8!, {r4-r6}
+
+	/* c1 and c2 registers */
+	mrc	p15, 0, r4, c1, c0, 2		@ CPACR
+	mrc	p15, 0, r5, c2, c0, 0		@ TTBR0
+	mrc	p15, 0, r6, c2, c0, 1		@ TTBR1
+	mrc	p15, 0, r7, c2, c0, 2		@ TTBCR
+	stmia	r8!, {r4-r7}
+
+	/* c3 and c10 registers */
+	mrc	p15, 0, r4, c3, c0, 0		@ DACR
+	mrc	p15, 0, r5, c10, c2, 0		@ PRRR
+	mrc	p15, 0, r6, c10, c2, 1		@ NMRR
+	stmia	r8!,{r4-r6}
+
+	/* c12, c13 and CPSR registers */
+	mrc	p15, 0, r4, c13, c0, 1		@ Context ID
+	mrc	p15, 0, r5, c13, c0, 2		@ User r/w thread ID
+	mrc	p15, 0, r6, c12, c0, 0		@ Secure or NS VBAR
+	mrs	r7, cpsr			@ Store CPSR
+	stmia	r8!, {r4-r7}
+
+	/* c1 control register */
+	mrc	p15, 0, r4, c1, c0, 0		@ Save control register
+	stmia	r8!, {r4}
+
+	/*
+	 * Flush all data from the L1 data cache before disabling
+	 * SCTLR.C bit.
+	 */
+	bl	v7_flush_dcache_all
+
+	/*
+	 * Clear the SCTLR.C bit to prevent further data cache
+	 * allocation. Clearing SCTLR.C would make all the data accesses
+	 * strongly ordered and would not hit the cache.
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #(1 << 2)		@ Disable the C bit
+	mcr	p15, 0, r0, c1, c0, 0
+	isb
+
+	/*
+	 * Invalidate L1 data cache. Even though only invalidate is
+	 * necessary exported flush API is used here. Doing clean
+	 * on already clean cache would be almost NOP.
+	 */
+	bl	v7_flush_dcache_all
+
+	/*
+	 * Switch the CPU from Symmetric Multiprocessing (SMP) mode
+	 * to AsymmetricMultiprocessing (AMP) mode by programming
+	 * the SCU power status to DORMANT or OFF mode.
+	 * This enables the CPU to be taken out of coherency by
+	 * preventing the CPU from receiving cache, TLB, or BTB
+	 * maintenance operations broadcast by other CPUs in the cluster.
+	 */
+	bl	omap4_get_sar_ram_base
+	mov	r8, r0
+	mrc	p15, 0, r0, c0, c0, 5		@ Read MPIDR
+	ands	r0, r0, #0x0f
+	ldreq	r1, [r8, #SCU_OFFSET0]
+	ldrne	r1, [r8, #SCU_OFFSET1]
+	bl	omap4_get_scu_base
+	bl     scu_power_mode
+
+do_WFI:
+	/*
+	 * Execute an ISB instruction to ensure that all of the
+	 * CP15 register changes have been committed.
+	 */
+	isb
+
+	/*
+	 * Execute a barrier instruction to ensure that all cache,
+	 * TLB and branch predictor maintenance operations issued
+	 * by any CPU in the cluster have completed.
+	 */
+	dsb
+	dmb
+
+	/*
+	 * Execute a WFI instruction and wait until the
+	 * STANDBYWFI output is asserted to indicate that the
+	 * CPU is in idle and low power state.
+	 */
+	wfi					@ Wait For Interrupt
+
+	/*
+	 * CPU is here when it failed to enter OFF/DORMANT or
+	 * no low power state was attempted.
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	tst	r0, #(1 << 2)			@ Check C bit enabled?
+	orreq	r0, r0, #(1 << 2)		@ Enable the C bit
+	mcreq	p15, 0, r0, c1, c0, 0
+	isb
+
+	/*
+	 * Ensure the CPU power state is set to NORMAL in
+	 * SCU power state so that CPU is back in coherency.
+	 * In non-coherent mode CPU can lock-up and lead to
+	 * system deadlock.
+	 */
+	bl	omap4_get_scu_base
+	mov	r1, #SCU_PM_NORMAL
+	bl     scu_power_mode
+	isb
+	dsb
+
+	ldmfd	sp!, {r0-r12, pc}		@ Restore regs and return
+ENDPROC(omap4_cpu_suspend)
+
+/*
+ * ============================
+ * == CPU resume entry point ==
+ * ============================
+ *
+ * void omap4_cpu_resume(void)
+ *
+ * ROM code jumps to this function while waking up from CPU
+ * OFF or DORMANT state. Physical address of the function is
+ * stored in the SAR RAM while entering to OFF or DORMANT mode.
+ */
+
+ENTRY(omap4_cpu_resume)
+	/*
+	 * Check the wakeup cpuid and use appropriate
+	 * SAR BANK location for context restore.
+	 */
+	ldr	r3, =OMAP44XX_SAR_RAM_BASE
+	mov	r1, #0
+	mcr	p15, 0, r1, c7, c5, 0		@ Invalidate L1 I
+	mrc	p15, 0, r0, c0, c0, 5		@ MPIDR
+	ands	r0, r0, #0x0f
+	orreq	r3, r3, #CPU0_SAVE_OFFSET
+	orrne	r3, r3, #CPU1_SAVE_OFFSET
+
+	/* Restore cp15 registers */
+	ldmia	r3!, {r4-r6}
+	mov	sp, r4				@ Restore sp
+	msr	spsr_cxsf, r5			@ Restore spsr
+	mov	lr, r6				@ Restore lr
+
+	/* c1 and c2 registers */
+	ldmia	r3!, {r4-r7}
+	mcr	p15, 0, r4, c1, c0, 2		@ CPACR
+	mcr	p15, 0, r5, c2, c0, 0		@ TTBR0
+	mcr	p15, 0, r6, c2, c0, 1		@ TTBR1
+	mcr	p15, 0, r7, c2, c0, 2		@ TTBCR
+
+	/* c3 and c10 registers */
+	ldmia	r3!,{r4-r6}
+	mcr	p15, 0, r4, c3, c0, 0		@ DACR
+	mcr	p15, 0, r5, c10, c2, 0		@ PRRR
+	mcr	p15, 0, r6, c10, c2, 1		@ NMRR
+
+	/* c12, c13 and CPSR registers */
+	ldmia	r3!,{r4-r7}
+	mcr	p15, 0, r4, c13, c0, 1		@ Context ID
+	mcr	p15, 0, r5, c13, c0, 2		@ User r/w thread ID
+	mrc	p15, 0, r6, c12, c0, 0		@ Secure or NS VBAR
+	msr	cpsr, r7			@ store cpsr
+
+	/*
+	 * Enabling MMU here. Page entry needs to be altered
+	 * to create temporary 1:1 map and then resore the entry
+	 * ones MMU is enabled
+	 */
+	mrc	p15, 0, r7, c2, c0, 2		@ Read TTBRControl
+	and	r7, #0x7			@ Extract N (0:2) to decide
+	cmp	r7, #0x0			@ TTBR0/TTBR1
+	beq	use_ttbr0
+ttbr_error:
+	b	ttbr_error			@ Only N = 0 supported
+use_ttbr0:
+	mrc	p15, 0, r2, c2, c0, 0		@ Read TTBR0
+	ldr	r5, =TTRBIT_MASK
+	and	r2, r5
+	mov	r4, pc
+	ldr	r5, =TABLE_INDEX_MASK
+	and	r4, r5				@ r4 = 31 to 20 bits of pc
+	ldr	r1, =TABLE_ENTRY
+	add	r1, r1, r4			@ r1 has value of table entry
+	lsr	r4, #18				@ Address of table entry
+	add	r2, r4				@ r2 - location to be modified
+
+	/* Ensure the modified entry makes it to main memory */
+#ifdef CONFIG_CACHE_L2X0
+	ldr	r5, =OMAP44XX_L2CACHE_BASE
+	str	r2, [r5, #L2X0_CLEAN_INV_LINE_PA]
+wait_l2:
+	ldr	r0, [r5, #L2X0_CLEAN_INV_LINE_PA]
+	ands	r0, #1
+	bne	wait_l2
+#endif
+
+	/* Storing previous entry of location being modified */
+	ldr     r5, =OMAP44XX_SAR_RAM_BASE
+	ldr	r4, [r2]
+	str	r4, [r5, #MMU_OFFSET]		@ Modify the table entry
+	str	r1, [r2]
+
+	/*
+	 * Storing address of entry being modified
+	 * It will be restored after enabling MMU
+	 */
+	ldr     r5, =OMAP44XX_SAR_RAM_BASE
+	orr	r5, r5, #MMU_OFFSET
+	str	r2, [r5, #TABLE_ADDRESS_OFFSET]
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 4		@ Flush prefetch buffer
+	mcr	p15, 0, r0, c7, c5, 6		@ Invalidate BTB
+	mcr	p15, 0, r0, c8, c5, 0		@ Invalidate ITLB
+	mcr	p15, 0, r0, c8, c6, 0		@ Invalidate DTLB
+
+	/*
+	 * Restore control register  but don't enable Data caches here.
+	 * Caches will be enabled after restoring MMU table entry.
+	 */
+	ldmia	r3!, {r4}
+	str	r4, [r5, #CR_VALUE_OFFSET]	@ Store previous value of CR
+	ldr	r2, =CACHE_DISABLE_MASK
+	and	r4, r2
+	mcr	p15, 0, r4, c1, c0, 0
+	isb
+	dsb
+	ldr	r0, =mmu_on_label
+	bx	r0
+mmu_on_label:
+	/* Set up the per-CPU stacks */
+	bl	cpu_init
+
+	/*
+	 * Restore the MMU table entry that was modified for
+	 * enabling MMU.
+	 */
+	bl	omap4_get_sar_ram_base
+	mov	r8, r0
+	orr	r8, r8, #MMU_OFFSET		@ Get address of entry that..
+	ldr	r2, [r8, #TABLE_ADDRESS_OFFSET]	@ was modified
+	ldr	r3, =local_va2pa_offet
+	add	r2, r2, r3
+	ldr	r0, [r8]			@ Get the previous value..
+	str	r0, [r2]			@ which needs to be restored
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c1, 6		@ flush TLB and issue barriers
+	mcr	p15, 0, r0, c7, c5, 4		@ Flush prefetch buffer
+	mcr	p15, 0, r0, c7, c5, 6		@ Invalidate BTB
+	mcr	p15, 0, r0, c8, c5, 0		@ Invalidate ITLB
+	mcr	p15, 0, r0, c8, c6, 0		@ Invalidate DTLB
+	dsb
+	isb
+	ldr	r0, [r8, #CR_VALUE_OFFSET]	@ Restore the Control register
+	mcr     p15, 0, r0, c1, c0, 0		@ with caches enabled.
+	isb
+
+	ldmfd	sp!, {r0-r12, pc}		@ restore regs and return
+
+	.equ	local_va2pa_offet, (PHYS_OFFSET + PAGE_OFFSET)
+
+ENDPROC(omap4_cpu_resume)
+
+#endif
-- 
1.6.0.4

[pm-core][PATCH v3 06/21] OMAP4: PM: Initialise all the clockdomains to supported states

[Santosh Shilimkar]

Initialise hardware supervised mode for all clockdomains if it's
supported. Initiate sleep transition for other clockdomains,
if they are not being used.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/pm44xx.c |   22 +++++++++++++++++++++-
 1 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 5b631f5..4f932f3 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -16,9 +16,11 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 
-#include "powerdomain.h"
 #include <mach/omap4-common.h>
 
+#include "powerdomain.h"
+#include "clockdomain.h"
+
 struct power_state {
 	struct powerdomain *pwrdm;
 	u32 next_state;
@@ -73,6 +75,22 @@ static const struct platform_suspend_ops omap_pm_ops = {
 };
 #endif /* CONFIG_SUSPEND */
 
+/*
+ * Enable hardware supervised mode for all clockdomains if it's
+ * supported. Initiate sleep transition for other clockdomains, if
+ * they are not used
+ */
+static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+{
+	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+		clkdm_allow_idle(clkdm);
+	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+			atomic_read(&clkdm->usecount) == 0)
+		clkdm_sleep(clkdm);
+	return 0;
+}
+
+
 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 {
 	struct power_state *pwrst;
@@ -111,6 +129,8 @@ static int __init omap4_pm_init(void)
 		goto err2;
 	}
 
+	(void) clkdm_for_each(clkdms_setup, NULL);
+
 	ret = omap4_mpuss_init();
 	if (ret) {
 		pr_err("Failed to initialise OMAP4 MPUSS\n");
-- 
1.6.0.4

[pm-core][PATCH v3 07/21] OMAP4: PM: Program CPU1 to hit OFF when off-lined

[Santosh Shilimkar]

Program non-boot CPUs to hit lowest supported power state
when it is off-lined using cpu hotplug framework.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/omap-hotplug.c |   18 +++++++++++++-----
 1 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 4976b93..9f8f097 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -20,6 +20,9 @@
 
 #include <asm/cacheflush.h>
 #include <mach/omap4-common.h>
+#include <mach/omap-wakeupgen.h>
+
+#include "powerdomain.h"
 
 int platform_cpu_kill(unsigned int cpu)
 {
@@ -32,6 +35,8 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
+	unsigned int this_cpu;
+
 	flush_cache_all();
 	dsb();
 
@@ -39,18 +44,21 @@ void platform_cpu_die(unsigned int cpu)
 	 * we're ready for shutdown now, so do it
 	 */
 	if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
-		printk(KERN_CRIT "Secure clear status failed\n");
+		pr_err("Secure clear status failed\n");
 
 	for (;;) {
 		/*
-		 * Execute WFI
+		 * Enter into low power state
+		 * clear all interrupt wakeup sources
 		 */
-		do_wfi();
-
-		if (omap_read_auxcoreboot0() == cpu) {
+		omap_wakeupgen_irqmask_all(cpu, 1);
+		omap4_enter_lowpower(cpu, PWRDM_POWER_OFF);
+		this_cpu = hard_smp_processor_id();
+		if (omap_read_auxcoreboot0() == this_cpu) {
 			/*
 			 * OK, proper wakeup, we're done
 			 */
+			omap_wakeupgen_irqmask_all(this_cpu, 0);
 			break;
 		}
 		pr_debug("CPU%u: spurious wakeup call\n", cpu);
-- 
1.6.0.4

[pm-core][PATCH v3 08/21] OMAP4: PM: CPU1 wakeup workaround from Low power modes

[Santosh Shilimkar]

The SGI(Software Generated Interrupts) are not wakeup capable from
low power states. This is known limitation on OMAP4 and needs to be
worked around by using software forced clockdomain wake-up. CPU0 forces
the CPU1 clockdomain to software force wakeup. After the wakeup, CPU1
restores its clockdomain hardware supervised mode.

More details can be found in OMAP4430 TRM - Version J
Section :
	4.3.4.2 Power States of CPU0 and CPU1

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/omap-hotplug.c |    8 ++++++++
 arch/arm/mach-omap2/omap-smp.c     |   26 +++++++++++++++++++++++++-
 2 files changed, 33 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 9f8f097..fe2dae1 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -23,6 +23,7 @@
 #include <mach/omap-wakeupgen.h>
 
 #include "powerdomain.h"
+#include "clockdomain.h"
 
 int platform_cpu_kill(unsigned int cpu)
 {
@@ -36,6 +37,10 @@ int platform_cpu_kill(unsigned int cpu)
 void platform_cpu_die(unsigned int cpu)
 {
 	unsigned int this_cpu;
+	static struct clockdomain *cpu1_clkdm;
+
+	if (!cpu1_clkdm)
+		cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
 
 	flush_cache_all();
 	dsb();
@@ -59,6 +64,9 @@ void platform_cpu_die(unsigned int cpu)
 			 * OK, proper wakeup, we're done
 			 */
 			omap_wakeupgen_irqmask_all(this_cpu, 0);
+
+			/* Restore clockdomain to hardware supervised */
+			clkdm_allow_idle(cpu1_clkdm);
 			break;
 		}
 		pr_debug("CPU%u: spurious wakeup call\n", cpu);
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 4fcaa4a..1230c4e 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -25,6 +25,8 @@
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
 
+#include "clockdomain.h"
+
 /* SCU base address */
 static void __iomem *scu_base;
 
@@ -54,6 +56,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+	static struct clockdomain *cpu1_clkdm;
+	static bool booted;
 	/*
 	 * Set synchronisation state between this boot processor
 	 * and the secondary one
@@ -69,7 +73,27 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	omap_modify_auxcoreboot0(0x200, 0xfffffdff);
 	flush_cache_all();
 	smp_wmb();
-	smp_cross_call(cpumask_of(cpu), 1);
+
+	if (!cpu1_clkdm)
+		cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
+
+	/*
+	 * The SGI(Software Generated Interrupts) are not wakeup capable
+	 * from low power states. This is known limitation on OMAP4 and
+	 * needs to be worked around by using software forced clockdomain
+	 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
+	 * software force wakeup. After the wakeup, CPU1 restores its
+	 * clockdomain hardware supervised mode.
+	 * More details can be found in OMAP4430 TRM - Version J
+	 * Section :
+	 *	4.3.4.2 Power States of CPU0 and CPU1
+	 */
+	if (booted) {
+		clkdm_wakeup(cpu1_clkdm);
+	} else {
+		dsb_sev();
+		booted = true;
+	}
 
 	/*
 	 * Now the secondary core is starting up let it run its
-- 
1.6.0.4

[pm-core][PATCH v3 09/21] OMAP4: PM: Add GIC distributor and interface enable/disable accessory API

[Santosh Shilimkar]

The power management code needs to have access to enable/disable the
gic cpu interface and distributor based on targetted low power
states.

These APIs are suppose to me moved to common ARM GIC library and patch
for the same was posted earlier. The GIC code refactoring is ongoing
and hence for time being this is kept under OMAP code so that OMAP4
PM can continue to work.

Discussion thread:
	http://www.mail-archive.com/linux-omap at vger.kernel.org/msg42940.html

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap2/include/mach/omap4-common.h |    5 +++-
 arch/arm/mach-omap2/omap4-common.c              |   24 +++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index a6ce905..a4b3beb 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -44,6 +44,10 @@ extern void __iomem *omap4_get_gic_dist_base(void);
 extern void __iomem *omap4_get_gic_cpu_base(void);
 extern void __iomem *omap4_get_sar_ram_base(void);
 extern void __init gic_init_irq(void);
+extern void gic_cpu_enable(void);
+extern void gic_cpu_disable(void);
+extern void gic_dist_enable(void);
+extern void gic_dist_disable(void);
 extern void omap_smc1(u32 fn, u32 arg);
 
 /*
@@ -64,7 +68,6 @@ extern int omap4_mpuss_init(void);
 extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
 extern void omap4_cpu_suspend(unsigned int cpu, unsigned int save_state);
 extern void omap4_cpu_resume(void);
-
 #else
 
 static inline int omap4_enter_lowpower(unsigned int cpu,
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 97d7d8a..9dd50b7 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -61,6 +61,30 @@ void __init gic_init_irq(void)
 	gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
 }
 
+/*
+ * FIXME: Remove this GIC APIs once common GIG library starts
+ * supporting it.
+ */
+void gic_cpu_enable(void)
+{
+	__raw_writel(0xf0, gic_cpu_base + GIC_CPU_PRIMASK);
+	__raw_writel(1, gic_cpu_base + GIC_CPU_CTRL);
+}
+
+void gic_cpu_disable(void)
+{
+	__raw_writel(0, gic_cpu_base + GIC_CPU_CTRL);
+}
+
+void gic_dist_enable(void)
+{
+	__raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
+}
+void gic_dist_disable(void)
+{
+	__raw_writel(0, gic_dist_base_addr + GIC_CPU_CTRL);
+}
+
 #ifdef CONFIG_CACHE_L2X0
 
 void __iomem *omap4_get_l2cache_base(void)
-- 
1.6.0.4

[pm-core][PATCH v3 10/21] OMAP4: PM: Add GIC save/restore support

[Santosh Shilimkar]

On OMAP4 when attempting MPU off-mode or OSWR, the GIC context is
lost. This patch adds GIC context save and restore support.

The context save is done by software and restore is done by
ROM code from predefined SAR locations where the context supposed
to be saved. Refer to OMAP4430 TRM for the SAR RAM layout.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/omap-hotplug.c         |    4 +
 arch/arm/mach-omap2/omap4-mpuss-lowpower.c |  195 +++++++++++++++++++++++++++-
 arch/arm/mach-omap2/omap4-sar-layout.h     |   20 +++
 3 files changed, 213 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index fe2dae1..f69cd5c 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -19,6 +19,8 @@
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+
 #include <mach/omap4-common.h>
 #include <mach/omap-wakeupgen.h>
 
@@ -57,6 +59,7 @@ void platform_cpu_die(unsigned int cpu)
 		 * clear all interrupt wakeup sources
 		 */
 		omap_wakeupgen_irqmask_all(cpu, 1);
+		gic_cpu_disable();
 		omap4_enter_lowpower(cpu, PWRDM_POWER_OFF);
 		this_cpu = hard_smp_processor_id();
 		if (omap_read_auxcoreboot0() == this_cpu) {
@@ -64,6 +67,7 @@ void platform_cpu_die(unsigned int cpu)
 			 * OK, proper wakeup, we're done
 			 */
 			omap_wakeupgen_irqmask_all(this_cpu, 0);
+			gic_cpu_enable();
 
 			/* Restore clockdomain to hardware supervised */
 			clkdm_allow_idle(cpu1_clkdm);
diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
index 21c5ad3..446b956 100644
--- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
@@ -47,6 +47,8 @@
 #include <asm/tlbflush.h>
 #include <asm/smp_scu.h>
 #include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/hardware/gic.h>
 
 #include <plat/omap44xx.h>
 #include <mach/omap4-common.h>
@@ -57,13 +59,41 @@
 
 #ifdef CONFIG_SMP
 
+#define GIC_MASK_ALL			0x0
+#define GIC_ISR_NON_SECURE		0xffffffff
+#define SPI_ENABLE_SET_OFFSET		0x04
+#define PPI_PRI_OFFSET			0x1c
+#define SPI_PRI_OFFSET			0x20
+#define SPI_TARGET_OFFSET		0x20
+#define SPI_CONFIG_OFFSET		0x20
+
+/* GIC save SAR bank base */
+static struct powerdomain *mpuss_pd;
+
+/* Variables to store maximum spi(Shared Peripheral Interrupts) registers. */
+static u32 max_spi_irq, max_spi_reg;
+
 struct omap4_cpu_pm_info {
 	struct powerdomain *pwrdm;
 	void __iomem *scu_sar_addr;
 };
 
+static void __iomem *gic_dist_base;
+static void __iomem *sar_base;
+
 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
 
+/* Helper functions */
+static inline void sar_writel(u32 val, u32 offset, u8 idx)
+{
+	__raw_writel(val, sar_base + offset + 4 * idx);
+}
+
+static inline u32 gic_readl(u32 offset, u8 idx)
+{
+	return __raw_readl(gic_dist_base + offset + 4 * idx);
+}
+
 /*
  * Set the CPUx powerdomain's previous power state
  */
@@ -121,6 +151,85 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
 }
 
 /*
+ * Save GIC context in SAR RAM. Restore is done by ROM code
+ * GIC is lost only when MPU hits OSWR or OFF. It consists
+ * of a distributor and a per-CPU interface module. The GIC
+ * save restore is optimised to save only necessary registers.
+ */
+static void gic_save_context(void)
+{
+	u8 i;
+	u32 val;
+
+	/*
+	 * Interrupt Clear Enable registers are inverse of set enable
+	 * and hence not needed to be saved. ROM code programs it
+	 * based on Set Enable register values.
+	 */
+
+	/* Save CPU 0 Interrupt Set Enable register */
+	val = gic_readl(GIC_DIST_ENABLE_SET, 0);
+	sar_writel(val, ICDISER_CPU0_OFFSET, 0);
+
+	/* Disable interrupts on CPU1 */
+	sar_writel(GIC_MASK_ALL, ICDISER_CPU1_OFFSET, 0);
+
+	/* Save all SPI Set Enable register */
+	for (i = 0; i < max_spi_reg; i++) {
+		val = gic_readl(GIC_DIST_ENABLE_SET + SPI_ENABLE_SET_OFFSET, i);
+		sar_writel(val, ICDISER_SPI_OFFSET, i);
+	}
+
+	/*
+	 * Interrupt Priority Registers
+	 * Secure sw accesses, last 5 bits of the 8 bits (bit[7:3] are used)
+	 * Non-Secure sw accesses, last 4 bits (i.e. bits[7:4] are used)
+	 * But the Secure Bits[7:3] are shifted by 1 in Non-Secure access.
+	 * Secure (bits[7:3] << 1)== Non Secure bits[7:4]
+	 * Hence right shift the value by 1 while saving the priority
+	 */
+
+	/* Save SGI priority registers (Software Generated Interrupt) */
+	for (i = 0; i < 4; i++) {
+		val = gic_readl(GIC_DIST_PRI, i);
+
+		/* Save the priority bits of the Interrupts */
+		sar_writel(val >> 0x1, ICDIPR_SFI_CPU0_OFFSET, i);
+
+		/* Disable the interrupts on CPU1 */
+		sar_writel(GIC_MASK_ALL, ICDIPR_SFI_CPU1_OFFSET, i);
+	}
+
+	/* Save PPI priority registers (Private Peripheral Intterupts) */
+	val = gic_readl(GIC_DIST_PRI + PPI_PRI_OFFSET, 0);
+	sar_writel(val >> 0x1, ICDIPR_PPI_CPU0_OFFSET, 0);
+	sar_writel(GIC_MASK_ALL, ICDIPR_PPI_CPU1_OFFSET, 0);
+
+	/* SPI priority registers - 4 interrupts/register */
+	for (i = 0; i < (max_spi_irq / 4); i++) {
+		val = gic_readl((GIC_DIST_PRI + SPI_PRI_OFFSET), i);
+		sar_writel(val >> 0x1, ICDIPR_SPI_OFFSET, i);
+	}
+
+	/* SPI Interrupt Target registers - 4 interrupts/register */
+	for (i = 0; i < (max_spi_irq / 4); i++) {
+		val = gic_readl((GIC_DIST_TARGET + SPI_TARGET_OFFSET), i);
+		sar_writel(val, ICDIPTR_SPI_OFFSET, i);
+	}
+
+	/* SPI Interrupt Congigeration eegisters- 16 interrupts/register */
+	for (i = 0; i < (max_spi_irq / 16); i++) {
+		val = gic_readl((GIC_DIST_CONFIG + SPI_CONFIG_OFFSET), i);
+		sar_writel(val, ICDICFR_OFFSET, i);
+	}
+
+	/* Set the Backup Bit Mask status for GIC */
+	val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+	val |= (SAR_BACKUP_STATUS_GIC_CPU0 | SAR_BACKUP_STATUS_GIC_CPU1);
+	__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+}
+
+/*
  * OMAP4 MPUSS Low Power Entry Function
  *
  * The purpose of this function is to manage low power programming
@@ -128,11 +237,25 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
  * Paramenters:
  *	cpu : CPU ID
  *	power_state: Targetted Low power state.
+ *
+ * MPUSS Low power states
+ * The basic rule is that the MPUSS power domain must be@the higher or
+ * equal power state (state that consume more power) than the higher of the
+ * two CPUs. For example, it is illegal for system power to be OFF, while
+ * the power of one or both of the CPU is DORMANT. When an illegal state is
+ * entered, then the hardware behavior is unpredictable.
+ *
+ * MPUSS state for the context save
+ * save_state =
+ *	0 - Nothing lost and no need to save: MPUSS INACTIVE
+ *	1 - CPUx L1 and logic lost: MPUSS CSWR
+ *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
+ *	3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
  */
 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 {
 	unsigned int save_state = 0;
-	unsigned int wakeup_cpu = hard_smp_processor_id();
+	unsigned int wakeup_cpu;
 
 	if ((cpu >= NR_CPUS) || (omap_rev() == OMAP4430_REV_ES1_0))
 		goto ret;
@@ -157,6 +280,23 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 		goto ret;
 	}
 
+	/*
+	 * MPUSS book keeping should be executed by master
+	 * CPU only which is also the last CPU to go down.
+	 */
+	if (cpu)
+		goto cpu_prepare;
+
+	/*
+	 * Check MPUSS next state and save GIC if needed
+	 * GIC lost during MPU OFF and OSWR
+	 */
+	if (pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_OFF) {
+		gic_save_context();
+		save_state = 3;
+	}
+
+cpu_prepare:
 	clear_cpu_prev_pwrst(cpu);
 	set_cpu_next_pwrst(cpu, power_state);
 	scu_pwrst_prepare(cpu, power_state);
@@ -177,6 +317,19 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 	wakeup_cpu = hard_smp_processor_id();
 	set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
 
+	/* If !master cpu return to hotplug-path */
+	if (wakeup_cpu)
+		goto ret;
+
+	/* Check MPUSS previous power state and enable GIC if needed */
+	if (pwrdm_read_prev_pwrst(mpuss_pd) == PWRDM_POWER_OFF) {
+		/* Clear SAR BACKUP status */
+		__raw_writel(0x0, sar_base + SAR_BACKUP_STATUS_OFFSET);
+		/* Enable GIC distributor and inteface on CPU0*/
+		gic_cpu_enable();
+		gic_dist_enable();
+	}
+
 ret:
 	return 0;
 }
@@ -187,7 +340,11 @@ ret:
 int __init omap4_mpuss_init(void)
 {
 	struct omap4_cpu_pm_info *pm_info;
-	void __iomem *sar_ram_base = omap4_get_sar_ram_base();
+	u8 i;
+
+	/* Get GIC and SAR RAM base addresses */
+	sar_base = omap4_get_sar_ram_base();
+	gic_dist_base = omap4_get_gic_dist_base();
 
 	if (omap_rev() == OMAP4430_REV_ES1_0) {
 		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -196,7 +353,7 @@ int __init omap4_mpuss_init(void)
 
 	/* Initilaise per CPU PM information */
 	pm_info = &per_cpu(omap4_pm_info, 0x0);
-	pm_info->scu_sar_addr = sar_ram_base + SCU_OFFSET0;
+	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
 	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
 	if (!pm_info->pwrdm) {
 		pr_err("Lookup failed for CPU0 pwrdm\n");
@@ -210,7 +367,7 @@ int __init omap4_mpuss_init(void)
 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 
 	pm_info = &per_cpu(omap4_pm_info, 0x1);
-	pm_info->scu_sar_addr = sar_ram_base + SCU_OFFSET1;
+	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
 	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
 	if (!pm_info->pwrdm) {
 		pr_err("Lookup failed for CPU1 pwrdm\n");
@@ -229,9 +386,35 @@ int __init omap4_mpuss_init(void)
 	 * is fixed so programit in init itself.
 	 */
 	__raw_writel(virt_to_phys(omap4_cpu_resume),
-			sar_ram_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
+			sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
 	__raw_writel(virt_to_phys(omap4_cpu_resume),
-			sar_ram_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET);
+			sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET);
+
+	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
+	if (!mpuss_pd) {
+		pr_err("Failed to get lookup for MPUSS pwrdm\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * Find out how many interrupts are supported.
+	 * OMAP4 supports max of 128 SPIs where as GIC can support
+	 * up to 1020 interrupt sources. On OMAP4, maximum SPIs are
+	 * fused in DIST_CTR bit-fields as 128. Hence the code is safe
+	 * from reserved register writes since its well within 1020.
+	 */
+	max_spi_reg = __raw_readl(gic_dist_base + GIC_DIST_CTR) & 0x1f;
+	max_spi_irq = max_spi_reg * 32;
+
+	/*
+	 * Mark the PPI and SPI interrupts as non-secure.
+	 * program the SAR locations for interrupt security registers to
+	 * reflect the same.
+	 */
+	sar_writel(GIC_ISR_NON_SECURE, ICDISR_CPU0_OFFSET, 0);
+	sar_writel(GIC_ISR_NON_SECURE, ICDISR_CPU1_OFFSET, 0);
+	for (i = 0; i < max_spi_reg; i++)
+		sar_writel(GIC_ISR_NON_SECURE, ICDISR_SPI_OFFSET, i);
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index 8b71b1e..baac4c0 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -30,4 +30,24 @@
 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET		0xa04
 #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET		0xa08
 
+/* GIC save restore offset from SAR_BANK3 */
+#define SAR_BACKUP_STATUS_OFFSET		(SAR_BANK3_OFFSET + 0x500)
+#define SAR_SECURE_RAM_SIZE_OFFSET		(SAR_BANK3_OFFSET + 0x504)
+#define SAR_SECRAM_SAVED_AT_OFFSET		(SAR_BANK3_OFFSET + 0x508)
+#define ICDISR_CPU0_OFFSET			(SAR_BANK3_OFFSET + 0x50c)
+#define ICDISR_CPU1_OFFSET			(SAR_BANK3_OFFSET + 0x510)
+#define ICDISR_SPI_OFFSET			(SAR_BANK3_OFFSET + 0x514)
+#define ICDISER_CPU0_OFFSET			(SAR_BANK3_OFFSET + 0x524)
+#define ICDISER_CPU1_OFFSET			(SAR_BANK3_OFFSET + 0x528)
+#define ICDISER_SPI_OFFSET			(SAR_BANK3_OFFSET + 0x52c)
+#define ICDIPR_SFI_CPU0_OFFSET			(SAR_BANK3_OFFSET + 0x53c)
+#define ICDIPR_PPI_CPU0_OFFSET			(SAR_BANK3_OFFSET + 0x54c)
+#define ICDIPR_SFI_CPU1_OFFSET			(SAR_BANK3_OFFSET + 0x550)
+#define ICDIPR_PPI_CPU1_OFFSET			(SAR_BANK3_OFFSET + 0x560)
+#define ICDIPR_SPI_OFFSET			(SAR_BANK3_OFFSET + 0x564)
+#define ICDIPTR_SPI_OFFSET			(SAR_BANK3_OFFSET + 0x5e4)
+#define ICDICFR_OFFSET				(SAR_BANK3_OFFSET + 0x664)
+#define SAR_BACKUP_STATUS_GIC_CPU0		0x1
+#define SAR_BACKUP_STATUS_GIC_CPU1		0x2
+
 #endif
-- 
1.6.0.4

[pm-core][PATCH v3 11/21] OMAP4: PM: Add WakeupGen save/restore support

[Santosh Shilimkar]

WakeupGen IP is integrated along with GIC to manage the
interrupt wakeups from CPU low power states. It's located in
always ON power domain. It manages masking/unmasking of
Shared peripheral interrupts(SPI).So the interrupt enable/disable
control should be in sync and consistent at WakeupGen and GIC so
that interrupts are not lost.

Considering this GIC and WakeupGen save and restore is done
together.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |    1 +
 arch/arm/mach-omap2/omap-wakeupgen.c              |   81 +++++++++++++++++++++
 arch/arm/mach-omap2/omap4-mpuss-lowpower.c        |    2 +
 arch/arm/mach-omap2/omap4-sar-layout.h            |   11 +++
 4 files changed, 95 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
index f10d106..66f31c3 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -37,4 +37,5 @@
 
 extern int __init omap_wakeupgen_init(void);
 extern void omap_wakeupgen_irqmask_all(unsigned int cpu, unsigned int set);
+extern void omap_wakeupgen_save(void);
 #endif
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index d9d2a3e..345a55c 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -24,6 +24,9 @@
 #include <asm/hardware/gic.h>
 
 #include <mach/omap-wakeupgen.h>
+#include <mach/omap4-common.h>
+
+#include "omap4-sar-layout.h"
 
 #define NR_BANKS		4
 #define MAX_IRQS		128
@@ -35,6 +38,7 @@
 
 /* WakeupGen Base addres */
 static void __iomem *wakeupgen_base;
+static void __iomem *sar_base;
 static DEFINE_PER_CPU(u32 [NR_BANKS], irqmasks);
 static DEFINE_SPINLOCK(wakeupgen_lock);
 
@@ -54,6 +58,11 @@ static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
 				(cpu * CPU_ENA_OFFSET) + (idx * 4));
 }
 
+static inline void sar_writel(u32 val, u32 offset, u8 idx)
+{
+	__raw_writel(val, sar_base + offset + (idx * 4));
+}
+
 static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
 {
 	u8 i;
@@ -236,3 +245,75 @@ int __init omap_wakeupgen_init(void)
 
 	return 0;
 }
+
+/**
+ * omap_wakeupgen_save() - WakeupGen context save function
+ *
+ * Save WakewupGen context in SAR BANK3. Restore is done by ROM code.
+ * WakeupGen IP is integrated along with GIC to manage the
+ * interrupt wakeups from CPU low power states. It's located in
+ * always ON power domain. It manages masking/unmasking of
+ * Shared peripheral interrupts(SPI).So the interrupt enable/disable
+ * control should be in sync and consistent at WakeupGen and GIC so
+ * that interrupts are not lost. Hence GIC and WakeupGen are saved
+ * and restored together.
+
+ * During normal operation, WakeupGen delivers external interrupts
+ * directly to the GIC. When the CPU asserts StandbyWFI, indicating
+ * it wants to enter lowpower state, the Standby Controller checks
+ * with the WakeupGen unit using the idlereq/idleack handshake to make
+ * sure there is no incoming interrupts.
+ */
+
+void omap_wakeupgen_save(void)
+{
+	u8 i;
+	u32 val;
+
+	if (omap_rev() == OMAP4430_REV_ES1_0)
+		return;
+
+	if (!sar_base)
+		sar_base = omap4_get_sar_ram_base();
+
+	for (i = 0; i < NR_BANKS; i++) {
+		/* Save the CPUx interrupt mask for IRQ 0 to 127 */
+		val = wakeupgen_readl(i, 0);
+		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
+		val = wakeupgen_readl(i, 1);
+		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
+
+		/*
+		 * Disable the secure interrupts for CPUx. The restore
+		 * code blindly restores secure and non-secure interrupt
+		 * masks from SAR RAM. Secure interrupts are not suppose
+		 * to be enabled from HLOS. So overwrite the SAR location
+		 * so that the secure interrupt remains disabled.
+		 */
+		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
+		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
+	}
+
+	/* Save AuxBoot* registers */
+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+	__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+	__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+
+	/* Save SyncReq generation logic */
+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+	__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+	__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+
+	/* Save SyncReq generation logic */
+	val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
+	__raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
+	val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
+	__raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
+
+	/* Set the Backup Bit Mask status */
+	val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
+	__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+}
diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
index 446b956..ddf5b72 100644
--- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
@@ -52,6 +52,7 @@
 
 #include <plat/omap44xx.h>
 #include <mach/omap4-common.h>
+#include <mach/omap-wakeupgen.h>
 
 #include "omap4-sar-layout.h"
 #include "pm.h"
@@ -292,6 +293,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 	 * GIC lost during MPU OFF and OSWR
 	 */
 	if (pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_OFF) {
+		omap_wakeupgen_save();
 		gic_save_context();
 		save_state = 3;
 	}
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index baac4c0..3f3e3c9 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -50,4 +50,15 @@
 #define SAR_BACKUP_STATUS_GIC_CPU0		0x1
 #define SAR_BACKUP_STATUS_GIC_CPU1		0x2
 
+/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
+#define WAKEUPGENENB_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x684)
+#define WAKEUPGENENB_SECURE_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x694)
+#define WAKEUPGENENB_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0x6a4)
+#define WAKEUPGENENB_SECURE_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0x6b4)
+#define AUXCOREBOOT0_OFFSET			(SAR_BANK3_OFFSET + 0x6c4)
+#define AUXCOREBOOT1_OFFSET			(SAR_BANK3_OFFSET + 0x6c8)
+#define PTMSYNCREQ_MASK_OFFSET			(SAR_BANK3_OFFSET + 0x6cc)
+#define PTMSYNCREQ_EN_OFFSET			(SAR_BANK3_OFFSET + 0x6d0)
+#define SAR_BACKUP_STATUS_WAKEUPGEN		0x10
+
 #endif
-- 
1.6.0.4

[pm-core][PATCH v3 12/21] OMAP4: PM: Add L2 cache lowpower support

[Santosh Shilimkar]

When MPUSS hits off-mode e, L2 cache is lost. This patch adds L2X0
necessary maintenance operations and context restoration in the
low power code.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/omap4-mpuss-lowpower.c |   18 ++++++++
 arch/arm/mach-omap2/omap4-sar-layout.h     |    2 +
 arch/arm/mach-omap2/sleep44xx.S            |   65 ++++++++++++++++++++++++++++
 3 files changed, 85 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
index ddf5b72..026c955 100644
--- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
@@ -49,6 +49,7 @@
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
 
 #include <plat/omap44xx.h>
 #include <mach/omap4-common.h>
@@ -336,6 +337,21 @@ ret:
 	return 0;
 }
 
+static void save_l2x0_auxctrl(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+	/*
+	 * Save the L2X0 AUXCTRL value to SAR memory. Its used to
+	 * in every restore patch MPUSS OFF path.
+	 */
+	void __iomem *l2x0_base = omap4_get_l2cache_base();
+	u32 val;
+
+	val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+	__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
+#endif
+}
+
 /*
  * Initialise OMAP4 MPUSS
  */
@@ -418,6 +434,8 @@ int __init omap4_mpuss_init(void)
 	for (i = 0; i < max_spi_reg; i++)
 		sar_writel(GIC_ISR_NON_SECURE, ICDISR_SPI_OFFSET, i);
 
+	save_l2x0_auxctrl();
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index 3f3e3c9..c72c0c5 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -25,6 +25,8 @@
 #define MMU_OFFSET				0xd00
 #define SCU_OFFSET0				0xd20
 #define SCU_OFFSET1				0xd24
+#define L2X0_OFFSET				0xd28
+#define L2X0_AUXCTRL_OFFSET			0xd2c
 
 /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET		0xa04
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index ccaf0e6..54fee44 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -13,6 +13,7 @@
 #include <asm/system.h>
 #include <asm/smp_scu.h>
 #include <asm/memory.h>
+#include <asm/hardware/cache-l2x0.h>
 
 #include <plat/omap44xx.h>
 #include <mach/omap4-common.h>
@@ -59,8 +60,10 @@ ENTRY(omap4_cpu_suspend)
 	cmp	r1, #0x0
 	beq	do_WFI				@ Nothing to save, jump to WFI
 	mov	r5, r0
+	mov	r6, r1
 	bl	omap4_get_sar_ram_base
 	mov	r8, r0
+	str	r6, [r8, #L2X0_OFFSET]		@ Store save state
 	ands	r5, r5, #0x0f
 	orreq	r8, r8, #CPU0_SAVE_OFFSET
 	orrne	r8, r8, #CPU1_SAVE_OFFSET
@@ -138,6 +141,42 @@ ENTRY(omap4_cpu_suspend)
 	ldrne	r1, [r8, #SCU_OFFSET1]
 	bl	omap4_get_scu_base
 	bl     scu_power_mode
+	isb
+	dsb
+
+#ifdef CONFIG_CACHE_L2X0
+	/*
+	 * Clean and invalidate the L2 cache.
+	 * Common cache-l2x0.c functions can't be used here since it
+	 * uses spinlocks. We are out of coherency here with data cache
+	 * disabled. The spinlock implementation uses exclusive load/store
+	 * instruction which can fail without data cache being enabled.
+	 * OMAP4 hardware doesn't support exclusive monitor which can
+	 * overcome exclusive access issue. Because of this, CPU can
+	 * lead to deadlock.
+	 */
+l2x_clean_inv:
+	bl	omap4_get_sar_ram_base
+	mov	r8, r0
+	ldr	r0, [r8, #L2X0_OFFSET]
+	cmp	r0, #3
+	bne	do_WFI
+	bl	omap4_get_l2cache_base
+	mov	r2, r0
+	mov	r0, #0xff
+	str	r0, [r2, #L2X0_CLEAN_WAY]
+wait:
+	ldr	r0, [r2, #L2X0_CLEAN_WAY]
+	ands	r0, r0, #0xff
+	bne	wait
+l2x_sync:
+	mov	r0, #0x0
+	str	r0, [r2, #L2X0_CACHE_SYNC]
+sync:
+	ldr	r0, [r2, #L2X0_CACHE_SYNC]
+	ands	r0, r0, #0x1
+	bne	sync
+#endif
 
 do_WFI:
 	/*
@@ -199,6 +238,32 @@ ENDPROC(omap4_cpu_suspend)
  */
 
 ENTRY(omap4_cpu_resume)
+#ifdef CONFIG_CACHE_L2X0
+	/*
+	 * Restore the L2 AUXCTRL and enable the L2 cache.
+	 * 0x109 =  Program the L2X0 AUXCTRL
+	 * 0x102 =  Enable the L2 using L2X0 CTRL
+	 * register r0 contains value to be programmed.
+	 * L2 cache is already invalidate by ROM code as part
+	 * of MPUSS OFF wakeup path.
+	 */
+	ldr	r2, =OMAP44XX_L2CACHE_BASE
+	ldr	r0, [r2, #L2X0_CTRL]
+	and	r0, #0x0f
+	cmp	r0, #1
+	beq	skip_l2en			@ Skip if already enabled
+	ldr	r3, =OMAP44XX_SAR_RAM_BASE
+	ldr	r0, [r3, #L2X0_AUXCTRL_OFFSET]
+	ldr	r12, =0x109			@ Setup L2 AUXCTRL value
+	dsb
+	smc	#0
+	mov	r0, #0x1
+	ldr	r12, =0x102			@ Enable L2 Cache controller
+	dsb
+	smc	#0
+skip_l2en:
+#endif
+
 	/*
 	 * Check the wakeup cpuid and use appropriate
 	 * SAR BANK location for context restore.
-- 
1.6.0.4

[pm-core][PATCH v3 13/21] OMAP4: suspend: Add MPUSS RET and OFF support

[Santosh Shilimkar]

This patch adds MPUSS(MPU Sub System) RET and OFF mode support
to suspend path. For both MPUSS RET and OFF support, CPUs are
programmed to OFF state.

Only MPUSS RET and OFF supported at this point of time. CORE RET
will be added subsequently.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/omap4-mpuss-lowpower.c |    6 ++-
 arch/arm/mach-omap2/pm44xx.c               |   67 ++++++++++++++++++++++++++--
 2 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
index 026c955..7348d29 100644
--- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
@@ -25,7 +25,7 @@
  *	ON(Inactive)	OFF		ON(Inactive)
  *	OFF		OFF		CSWR
  *	OFF		OFF		OSWR (*TBD)
- *	OFF		OFF		OFF* (*TBD)
+ *	OFF		OFF		OFF
  *	----------------------------------------------
  *
  * Note: CPU0 is the master core and it is the last CPU to go down
@@ -293,6 +293,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 	 * Check MPUSS next state and save GIC if needed
 	 * GIC lost during MPU OFF and OSWR
 	 */
+	pwrdm_clear_all_prev_pwrst(mpuss_pd);
 	if (pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_OFF) {
 		omap_wakeupgen_save();
 		gic_save_context();
@@ -414,6 +415,9 @@ int __init omap4_mpuss_init(void)
 		return -ENODEV;
 	}
 
+	/* Clear CPU previous power domain state */
+	pwrdm_clear_all_prev_pwrst(mpuss_pd);
+
 	/*
 	 * Find out how many interrupts are supported.
 	 * OMAP4 supports max of 128 SPIs where as GIC can support
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 4f932f3..051461c 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,8 +1,9 @@
 /*
  * OMAP4 Power Management Routines
  *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
  * Rajendra Nayak <rnayak@ti.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -35,7 +36,48 @@ static LIST_HEAD(pwrst_list);
 #ifdef CONFIG_SUSPEND
 static int omap4_pm_suspend(void)
 {
-	do_wfi();
+	struct power_state *pwrst;
+	int state, ret = 0;
+	u32 cpu_id = smp_processor_id();
+
+	/* Save current powerdomain state */
+	list_for_each_entry(pwrst, &pwrst_list, node) {
+		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
+	}
+
+	/* Set targeted power domain states by suspend */
+	list_for_each_entry(pwrst, &pwrst_list, node) {
+		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+	}
+
+	/*
+	 * For MPUSS to hit power domain retention(CSWR or OSWR),
+	 * CPU0 and CPU1 power domain needs to be in OFF or DORMANT
+	 * state. For MPUSS to reach off-mode. CPU0 and CPU1 power domain
+	 * should be in off state.
+	 * Only master CPU followes suspend path. All other CPUs follow
+	 * cpu-hotplug path in system wide suspend. On OMAP4, CPU power
+	 * domain CSWR is not supported by hardware.
+	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
+	 */
+	omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
+
+	/* Restore next powerdomain state */
+	list_for_each_entry(pwrst, &pwrst_list, node) {
+		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
+		if (state > pwrst->next_state) {
+			pr_info("Powerdomain (%s) didn't enter "
+			       "target state %d\n",
+			       pwrst->pwrdm->name, pwrst->next_state);
+			ret = -1;
+		}
+		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
+	}
+	if (ret)
+		pr_err("Could not enter target state in pm_suspend\n");
+	else
+		pr_err("Successfully put all powerdomains to target state\n");
+
 	return 0;
 }
 
@@ -98,14 +140,31 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 	if (!pwrdm->pwrsts)
 		return 0;
 
+	/*
+	 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
+	 * through hotplug path and CPU0 explicitly programmed
+	 * further down in the code path
+	 */
+	if ((!strcmp(pwrdm->name, "cpu0_pwrdm")) ||
+		(!strcmp(pwrdm->name, "cpu1_pwrdm")))
+		return 0;
+
+	/*
+	 * FIXME: Remove this check when core retention is supported
+	 * Only MPUSS power domain is added in the list.
+	 */
+	if (strcmp(pwrdm->name, "mpu_pwrdm"))
+		return 0;
+
 	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 	if (!pwrst)
 		return -ENOMEM;
+
 	pwrst->pwrdm = pwrdm;
-	pwrst->next_state = PWRDM_POWER_ON;
+	pwrst->next_state = PWRDM_POWER_OFF;
 	list_add(&pwrst->node, &pwrst_list);
 
-	return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state);
+	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 }
 
 /**
-- 
1.6.0.4

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

This patch adds configurable wakeup timer support in suspend. Also
for statistics pm counter support is added.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/omap4-mpuss-lowpower.c |    4 ++++
 arch/arm/mach-omap2/pm-debug.c             |   11 +++++++++--
 arch/arm/mach-omap2/pm44xx.c               |    6 ++++++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
index 7348d29..3cd9e8b 100644
--- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
@@ -289,6 +289,8 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 	if (cpu)
 		goto cpu_prepare;
 
+	pwrdm_pre_transition();
+
 	/*
 	 * Check MPUSS next state and save GIC if needed
 	 * GIC lost during MPU OFF and OSWR
@@ -334,6 +336,8 @@ cpu_prepare:
 		gic_dist_enable();
 	}
 
+	pwrdm_post_transition();
+
 ret:
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index a5a83b3..232623c 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -604,9 +604,11 @@ static int __init pm_dbg_init(void)
 	if (pm_dbg_init_done)
 		return 0;
 
-	if (cpu_is_omap34xx())
+	if (cpu_is_omap34xx()) {
 		pm_dbg_reg_modules = omap3_pm_reg_modules;
-	else {
+	} else if (cpu_is_omap44xx()) {
+		/* Allow pm_dbg_init on OMAP4. */
+	} else {
 		printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
 		return -ENODEV;
 	}
@@ -622,6 +624,9 @@ static int __init pm_dbg_init(void)
 
 	pwrdm_for_each(pwrdms_setup, (void *)d);
 
+	if (cpu_is_omap44xx())
+		goto skip_reg_debufs;
+
 	pm_dbg_dir = debugfs_create_dir("registers", d);
 	if (IS_ERR(pm_dbg_dir))
 		return PTR_ERR(pm_dbg_dir);
@@ -641,6 +646,8 @@ static int __init pm_dbg_init(void)
 				   &enable_off_mode, &pm_dbg_option_fops);
 	(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
 				   &sleep_while_idle, &pm_dbg_option_fops);
+
+skip_reg_debufs:
 	(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
 				   &wakeup_timer_seconds, &pm_dbg_option_fops);
 	(void) debugfs_create_file("wakeup_timer_milliseconds",
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 051461c..af3a56d 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -21,6 +21,7 @@
 
 #include "powerdomain.h"
 #include "clockdomain.h"
+#include "pm.h"
 
 struct power_state {
 	struct powerdomain *pwrdm;
@@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
 	int state, ret = 0;
 	u32 cpu_id = smp_processor_id();
 
+	/* Wakeup timer from suspend */
+	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
+		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
+					 wakeup_timer_milliseconds);
+
 	/* Save current powerdomain state */
 	list_for_each_entry(pwrst, &pwrst_list, node) {
 		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
-- 
1.6.0.4

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> --- a/arch/arm/mach-omap2/pm-debug.c
> +++ b/arch/arm/mach-omap2/pm-debug.c
> @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
>  	int state, ret = 0;
>  	u32 cpu_id = smp_processor_id();
>  
> +	/* Wakeup timer from suspend */
> +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> +					 wakeup_timer_milliseconds);
> +
>  	/* Save current powerdomain state */
>  	list_for_each_entry(pwrst, &pwrst_list, node) {
>  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);

This hack to mess diretly with sys_timer will be ripped out,
so please drop this patch.

In the long run we'll have dmtimer1 dedicated to the PM code,
so then it's possible to do similar things.

Tony

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Santosh Shilimkar]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Tuesday, March 29, 2011 2:31 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> timer and debug counters
>
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > --- a/arch/arm/mach-omap2/pm-debug.c
> > +++ b/arch/arm/mach-omap2/pm-debug.c
> > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> >  	int state, ret = 0;
> >  	u32 cpu_id = smp_processor_id();
> >
> > +	/* Wakeup timer from suspend */
> > +	if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > +		omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > +					 wakeup_timer_milliseconds);
> > +
> >  	/* Save current powerdomain state */
> >  	list_for_each_entry(pwrst, &pwrst_list, node) {
> >  		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> >pwrdm);
>
> This hack to mess diretly with sys_timer will be ripped out,
> so please drop this patch.
>
Ok.

> In the long run we'll have dmtimer1 dedicated to the PM code,
> so then it's possible to do similar things.
>

Regards,
Santosh

[pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup timer and debug counters

[Shilimkar, Santosh]

Sorry for spamming your inbox with same email. :(
Looks like my mailer has srewed up. It send same messege almost 20 times and
it shows me that it has
stuck in outbox

Regards
Santosh

On Tue, Mar 29, 2011 at 11:20 AM, Santosh Shilimkar <
santosh.shilimkar@ti.com> wrote:

> > -----Original Message-----
> > From: Tony Lindgren [mailto:tony at atomide.com]
> > Sent: Tuesday, March 29, 2011 2:31 AM
> > To: Santosh Shilimkar
> > Cc: linux-omap at vger.kernel.org; khilman at ti.com; rnayak at ti.com;
> > linux-arm-kernel at lists.infradead.org
> > Subject: Re: [pm-core][PATCH v3 14/21] OMAP4: pm-debug: Add wakeup
> > timer and debug counters
> >
> > * Santosh Shilimkar <santosh.shilimkar@ti.com> [110328 02:21]:
> > > --- a/arch/arm/mach-omap2/pm-debug.c
> > > +++ b/arch/arm/mach-omap2/pm-debug.c
> > > @@ -40,6 +41,11 @@ static int omap4_pm_suspend(void)
> > >     int state, ret = 0;
> > >     u32 cpu_id = smp_processor_id();
> > >
> > > +   /* Wakeup timer from suspend */
> > > +   if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> > > +           omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> > > +                                    wakeup_timer_milliseconds);
> > > +
> > >     /* Save current powerdomain state */
> > >     list_for_each_entry(pwrst, &pwrst_list, node) {
> > >             pwrst->saved_state = pwrdm_read_next_pwrst(pwrst-
> > >pwrdm);
> >
> > This hack to mess diretly with sys_timer will be ripped out,
> > so please drop this patch.
> >
> Ok.
>
> > In the long run we'll have dmtimer1 dedicated to the PM code,
> > so then it's possible to do similar things.
> >
>
> Regards,
> Santosh
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20110329/57b3038e/attachment-0001.html>

[pm-core][PATCH v3 15/21] OMAP4: cpuidle: Basic CPUidle support

[Santosh Shilimkar]

From: Rajendra Nayak <rnayak@ti.com>

The patch adds a basic CPUidle driver for OMAP4. Just
one C state is registered for CPU0 which does a WFI.
CPU1 is left with defualt idle and the low power state
for it is managed via cpu-hotplug.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/Makefile      |    3 +-
 arch/arm/mach-omap2/cpuidle44xx.c |  161 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/pm.h          |    1 +
 arch/arm/mach-omap2/pm44xx.c      |    2 +
 4 files changed, 166 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/cpuidle44xx.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8558215..eec783d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -64,7 +64,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o pm_bus.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o \
 					   cpuidle34xx.o pm_bus.o
 obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o \
-					   omap4-mpuss-lowpower.o sleep44xx.o
+					   omap4-mpuss-lowpower.o sleep44xx.o \
+					   cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
new file mode 100644
index 0000000..270404f
--- /dev/null
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -0,0 +1,161 @@
+/*
+ * OMAP4 CPU idle Routines
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/sched.h>
+#include <linux/cpuidle.h>
+
+#include <asm/proc-fns.h>
+
+#include <mach/omap4-common.h>
+
+#include "pm.h"
+
+#ifdef CONFIG_CPU_IDLE
+
+#define OMAP4_MAX_STATES	1
+/* C1 - CPU0 ON + + CPU1 ON + MPU ON + CORE ON */
+#define OMAP4_STATE_C1		0
+
+struct omap4_processor_cx {
+	u8 valid;
+	u8 type;
+	u32 sleep_latency;
+	u32 wakeup_latency;
+	u32 cpu0_state;
+	u32 mpu_state;
+	u32 core_state;
+	u32 threshold;
+	u32 flags;
+};
+
+struct omap4_processor_cx omap4_power_states[OMAP4_MAX_STATES];
+
+static struct cpuidle_params cpuidle_params_table[] = {
+	/* C1 */
+	{1, 2, 2, 5},
+};
+
+/**
+ * omap4_enter_idle - Programs OMAP4 to enter the specified state
+ * @dev: cpuidle device
+ * @state: The target state to be programmed
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified low power state selected by the governor.
+ * Returns the amount of time spent in the low power state.
+ */
+static int omap4_enter_idle(struct cpuidle_device *dev,
+			struct cpuidle_state *state)
+{
+	struct timespec ts_preidle, ts_postidle, ts_idle;
+
+	/* Used to keep track of the total time in idle */
+	getnstimeofday(&ts_preidle);
+
+	local_irq_disable();
+	local_fiq_disable();
+
+	cpu_do_idle();
+
+	getnstimeofday(&ts_postidle);
+	ts_idle = timespec_sub(ts_postidle, ts_preidle);
+
+	local_irq_enable();
+	local_fiq_enable();
+
+	return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
+}
+
+DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
+
+/**
+ * omap4_init_power_states - Initialises the OMAP4 specific C states.
+ *
+ * Below is the desciption of each C state.
+ * C1 : CPUx wfi + MPU inative + Core inactive
+ */
+void omap4_init_power_states(void)
+{
+	/*
+	 * C1 - CPU0 ON + + CPU1 ON + MPU ON + CORE ON
+	 */
+	omap4_power_states[OMAP4_STATE_C1].valid =
+			cpuidle_params_table[OMAP4_STATE_C1].valid;
+	omap4_power_states[OMAP4_STATE_C1].type = OMAP4_STATE_C1;
+	omap4_power_states[OMAP4_STATE_C1].sleep_latency =
+			cpuidle_params_table[OMAP4_STATE_C1].sleep_latency;
+	omap4_power_states[OMAP4_STATE_C1].wakeup_latency =
+			cpuidle_params_table[OMAP4_STATE_C1].wake_latency;
+	omap4_power_states[OMAP4_STATE_C1].threshold =
+			cpuidle_params_table[OMAP4_STATE_C1].threshold;
+	omap4_power_states[OMAP4_STATE_C1].mpu_state = PWRDM_POWER_ON;
+	omap4_power_states[OMAP4_STATE_C1].core_state = PWRDM_POWER_ON;
+	omap4_power_states[OMAP4_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
+
+}
+
+struct cpuidle_driver omap4_idle_driver = {
+	.name =		"omap4_idle",
+	.owner =	THIS_MODULE,
+};
+
+/**
+ * omap4_idle_init - Init routine for OMAP4 idle
+ *
+ * Registers the OMAP4 specific cpuidle driver with the cpuidle
+ * framework with the valid set of states.
+ */
+int __init omap4_idle_init(void)
+{
+	int cpu_id = 0, i, count = 0;
+	struct omap4_processor_cx *cx;
+	struct cpuidle_state *state;
+	struct cpuidle_device *dev;
+
+	omap4_init_power_states();
+	cpuidle_register_driver(&omap4_idle_driver);
+
+	dev = &per_cpu(omap4_idle_dev, cpu_id);
+	dev->cpu = cpu_id;
+	count = 0;
+	for (i = OMAP4_STATE_C1; i < OMAP4_MAX_STATES; i++) {
+		cx = &omap4_power_states[i];
+		state = &dev->states[count];
+
+		if (!cx->valid)
+			continue;
+		cpuidle_set_statedata(state, cx);
+		state->exit_latency = cx->sleep_latency +
+						cx->wakeup_latency;
+		state->target_residency = cx->threshold;
+		state->flags = cx->flags;
+		state->enter = omap4_enter_idle;
+		sprintf(state->name, "C%d", count+1);
+		count++;
+	}
+
+	if (!count)
+		return -EINVAL;
+	dev->state_count = count;
+
+	if (cpuidle_register_device(dev)) {
+		pr_err("%s: CPUidle register device failed\n", __func__);
+			return -EIO;
+		}
+
+	return 0;
+}
+#else
+int __init omap4_idle_init(void)
+{
+	return 0;
+}
+#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 797bfd1..b19d5b2 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -21,6 +21,7 @@ extern void omap_sram_idle(void);
 extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
+extern int omap4_idle_init(void);
 
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index af3a56d..b78417c 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -206,6 +206,8 @@ static int __init omap4_pm_init(void)
 	suspend_set_ops(&omap_pm_ops);
 #endif /* CONFIG_SUSPEND */
 
+	omap4_idle_init();
+
 err2:
 	return ret;
 }
-- 
1.6.0.4

[pm-core][PATCH v3 16/21] OMAP4: cpuidle: Add MPUSS RET OFF states

[Santosh Shilimkar]

This patch adds MPUSS low power states in cpuidle.

	C1 - CPU0 ON + CPU1 ON + MPU ON
	C2 - CPU0 ON + CPU1 OFF + MPU ON
	C3 - CPU0 OFF + CPU1 OFF + MPU CSWR
	C4 - CPU0 OFF + CPU1 OFF + MPU OFF

MPU OSWR isn't supported yet. To support OSWR, power domain context
registers needs to be managed which are not supported yet. A patch
to address this was submitted but it's not ready for merge yet because
it was not addressing all OMAP4 power domain context registers.
More info on this issue:
	http://www.mail-archive.com/linux-omap at vger.kernel.org/msg38667.html

OMAP4 powerdomain INACTIVE support is also dropped because of inconsistency
of it with OMAP3. More information  on this thread.
	http://www.spinics.net/lists/linux-omap/msg45370.html

CORE low power states and associated latencies will be updated as part
along with chip retention support.

On OMAP4 because of hardware constraints, no low power states are
targeted when both CPUs are online and in SMP mode. The low power
states are attempted only when secondary CPU gets offline to OFF
through hotplug infrastructure.

Thanks to Nicole Chalhoub <n-chalhoub@ti.com> for doing exhaustive
C-state latency profiling.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/cpuidle44xx.c |  129 +++++++++++++++++++++++++++++++++++--
 1 files changed, 124 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 270404f..19a405c 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2011 Texas Instruments, Inc.
  * Rajendra Nayak <rnayak@ti.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,12 +18,20 @@
 #include <mach/omap4-common.h>
 
 #include "pm.h"
+#include "prm.h"
 
 #ifdef CONFIG_CPU_IDLE
 
-#define OMAP4_MAX_STATES	1
+#define OMAP4_MAX_STATES	4
+
 /* C1 - CPU0 ON + + CPU1 ON + MPU ON + CORE ON */
 #define OMAP4_STATE_C1		0
+/* C2 - CPU0 ON + CPU1 OFF + MPU ON + CORE ON */
+#define OMAP4_STATE_C2		1
+/* C3 - CPU0 OFF + CPU1 OFF + MPU CSWR + CORE ON */
+#define OMAP4_STATE_C3		2
+/* C4 - CPU0 OFF + CPU1 OFF + MPU OFF + CORE ON */
+#define OMAP4_STATE_C4		3
 
 struct omap4_processor_cx {
 	u8 valid;
@@ -31,16 +40,34 @@ struct omap4_processor_cx {
 	u32 wakeup_latency;
 	u32 cpu0_state;
 	u32 mpu_state;
+	u32 mpu_logic_state;
 	u32 core_state;
+	u32 core_logic_state;
 	u32 threshold;
 	u32 flags;
+	const char *desc;
 };
 
 struct omap4_processor_cx omap4_power_states[OMAP4_MAX_STATES];
+static struct powerdomain *mpu_pd, *cpu1_pd, *core_pd;
 
+/*
+ * FIXME: Full latency numbers needs to be updated as part of
+ * cpuidle CORE retention support.
+ * Currently only MPUSS latency numbers are added based on
+ * measurements done internally. The numbers for MPUSS are
+ * not board dependent and hence set directly here instead of
+ * passing it from board files.
+ */
 static struct cpuidle_params cpuidle_params_table[] = {
-	/* C1 */
-	{1, 2, 2, 5},
+	/* C1 - CPU0 ON + CPU1 ON + MPU ON  + CORE ON */
+	{1,	2,	2,	5},
+	/* C2 - CPU0 ON + CPU1 OFF + MPU ON  + CORE ON */
+	{1,	140,	160,	300},
+	/* C3 - CPU0 OFF + CPU1 OFF + MPU CSWR + CORE ON */
+	{1,	200,	300,	700},
+	/* C4 - CPU0 OFF + CPU1 OFF + MPU OFF + CORE ON */
+	{1,	1400,	600,	5000},
 };
 
 /**
@@ -55,7 +82,9 @@ static struct cpuidle_params cpuidle_params_table[] = {
 static int omap4_enter_idle(struct cpuidle_device *dev,
 			struct cpuidle_state *state)
 {
+	struct omap4_processor_cx *cx = cpuidle_get_statedata(state);
 	struct timespec ts_preidle, ts_postidle, ts_idle;
+	u32 cpu1_state;
 
 	/* Used to keep track of the total time in idle */
 	getnstimeofday(&ts_preidle);
@@ -63,7 +92,26 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
 	local_irq_disable();
 	local_fiq_disable();
 
-	cpu_do_idle();
+	/*
+	 * Continue to do only WFI on CPU0 till CPU1 hits OFF state.
+	 * This is necessary to honour hardware recommondation
+	 * of triggeing all the possible low power modes once CPU1 is
+	 * out of coherency and in OFF mode.
+	 * Update dev->last_state so that governor stats reflects right
+	 * data.
+	 */
+	cpu1_state = pwrdm_read_pwrst(cpu1_pd);
+	if ((cpu1_state != PWRDM_POWER_OFF) || (!cx->valid)) {
+		dev->last_state = dev->safe_state;
+		cx = cpuidle_get_statedata(dev->safe_state);
+	}
+
+	pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
+	omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+	pwrdm_set_logic_retst(core_pd, cx->core_logic_state);
+	omap_set_pwrdm_state(core_pd, cx->core_state);
+
+	omap4_enter_lowpower(dev->cpu, cx->cpu0_state);
 
 	getnstimeofday(&ts_postidle);
 	ts_idle = timespec_sub(ts_postidle, ts_preidle);
@@ -96,9 +144,73 @@ void omap4_init_power_states(void)
 			cpuidle_params_table[OMAP4_STATE_C1].wake_latency;
 	omap4_power_states[OMAP4_STATE_C1].threshold =
 			cpuidle_params_table[OMAP4_STATE_C1].threshold;
+	omap4_power_states[OMAP4_STATE_C1].cpu0_state = PWRDM_POWER_ON;
 	omap4_power_states[OMAP4_STATE_C1].mpu_state = PWRDM_POWER_ON;
+	omap4_power_states[OMAP4_STATE_C1].mpu_logic_state = PWRDM_POWER_RET;
 	omap4_power_states[OMAP4_STATE_C1].core_state = PWRDM_POWER_ON;
+	omap4_power_states[OMAP4_STATE_C1].core_logic_state = PWRDM_POWER_RET;
 	omap4_power_states[OMAP4_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
+	omap4_power_states[OMAP4_STATE_C1].desc = "MPU ON + CORE ON";
+
+	/*
+	 * C2 - CPU0 ON + CPU1 OFF + MPU ON + CORE ON
+	 */
+	omap4_power_states[OMAP4_STATE_C2].valid =
+			cpuidle_params_table[OMAP4_STATE_C2].valid;
+	omap4_power_states[OMAP4_STATE_C2].type = OMAP4_STATE_C2;
+	omap4_power_states[OMAP4_STATE_C2].sleep_latency =
+			cpuidle_params_table[OMAP4_STATE_C2].sleep_latency;
+	omap4_power_states[OMAP4_STATE_C2].wakeup_latency =
+			cpuidle_params_table[OMAP4_STATE_C2].wake_latency;
+	omap4_power_states[OMAP4_STATE_C2].threshold =
+			cpuidle_params_table[OMAP4_STATE_C2].threshold;
+	omap4_power_states[OMAP4_STATE_C2].cpu0_state = PWRDM_POWER_ON;
+	omap4_power_states[OMAP4_STATE_C2].mpu_state = PWRDM_POWER_ON;
+	omap4_power_states[OMAP4_STATE_C2].mpu_logic_state = PWRDM_POWER_RET;
+	omap4_power_states[OMAP4_STATE_C2].core_state = PWRDM_POWER_ON;
+	omap4_power_states[OMAP4_STATE_C2].core_logic_state = PWRDM_POWER_RET;
+	omap4_power_states[OMAP4_STATE_C2].flags = CPUIDLE_FLAG_IGNORE;
+	omap4_power_states[OMAP4_STATE_C2].desc = "MPU ON + CORE ON";
+
+	/*
+	 * C3 - CPU0 OFF + CPU1 OFF + MPU CSWR + CORE ON
+	 */
+	omap4_power_states[OMAP4_STATE_C3].valid =
+			cpuidle_params_table[OMAP4_STATE_C3].valid;
+	omap4_power_states[OMAP4_STATE_C3].type = OMAP4_STATE_C3;
+	omap4_power_states[OMAP4_STATE_C3].sleep_latency =
+			cpuidle_params_table[OMAP4_STATE_C3].sleep_latency;
+	omap4_power_states[OMAP4_STATE_C3].wakeup_latency =
+			cpuidle_params_table[OMAP4_STATE_C3].wake_latency;
+	omap4_power_states[OMAP4_STATE_C3].threshold =
+			cpuidle_params_table[OMAP4_STATE_C3].threshold;
+	omap4_power_states[OMAP4_STATE_C3].cpu0_state = PWRDM_POWER_OFF;
+	omap4_power_states[OMAP4_STATE_C3].mpu_state = PWRDM_POWER_RET;
+	omap4_power_states[OMAP4_STATE_C3].mpu_logic_state = PWRDM_POWER_RET;
+	omap4_power_states[OMAP4_STATE_C3].core_state = PWRDM_POWER_ON;
+	omap4_power_states[OMAP4_STATE_C3].core_logic_state = PWRDM_POWER_RET;
+	omap4_power_states[OMAP4_STATE_C3].flags = CPUIDLE_FLAG_IGNORE;
+	omap4_power_states[OMAP4_STATE_C3].desc = "MPU CSWR + CORE ON";
+
+	/*
+	 * C4 - CPU0 OFF + CPU1 OFF + MPU OFF + CORE ON
+	 */
+	omap4_power_states[OMAP4_STATE_C4].valid =
+			cpuidle_params_table[OMAP4_STATE_C4].valid;
+	omap4_power_states[OMAP4_STATE_C4].type = OMAP4_STATE_C4;
+	omap4_power_states[OMAP4_STATE_C4].sleep_latency =
+			cpuidle_params_table[OMAP4_STATE_C4].sleep_latency;
+	omap4_power_states[OMAP4_STATE_C4].wakeup_latency =
+			cpuidle_params_table[OMAP4_STATE_C4].wake_latency;
+	omap4_power_states[OMAP4_STATE_C4].threshold =
+			cpuidle_params_table[OMAP4_STATE_C4].threshold;
+	omap4_power_states[OMAP4_STATE_C4].cpu0_state = PWRDM_POWER_OFF;
+	omap4_power_states[OMAP4_STATE_C4].mpu_state = PWRDM_POWER_OFF;
+	omap4_power_states[OMAP4_STATE_C4].mpu_logic_state = PWRDM_POWER_OFF;
+	omap4_power_states[OMAP4_STATE_C4].core_state = PWRDM_POWER_ON;
+	omap4_power_states[OMAP4_STATE_C4].core_logic_state = PWRDM_POWER_RET;
+	omap4_power_states[OMAP4_STATE_C4].flags = CPUIDLE_FLAG_IGNORE;
+	omap4_power_states[OMAP4_STATE_C4].desc = "MPU OFF + CORE ON";
 
 }
 
@@ -115,11 +227,15 @@ struct cpuidle_driver omap4_idle_driver = {
  */
 int __init omap4_idle_init(void)
 {
-	int cpu_id = 0, i, count = 0;
+	int cpu_id = 0, i, count = 0, ret;
 	struct omap4_processor_cx *cx;
 	struct cpuidle_state *state;
 	struct cpuidle_device *dev;
 
+	mpu_pd = pwrdm_lookup("mpu_pwrdm");
+	cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
+	core_pd = pwrdm_lookup("core_pwrdm");
+
 	omap4_init_power_states();
 	cpuidle_register_driver(&omap4_idle_driver);
 
@@ -137,8 +253,11 @@ int __init omap4_idle_init(void)
 						cx->wakeup_latency;
 		state->target_residency = cx->threshold;
 		state->flags = cx->flags;
+		if (cx->type == OMAP4_STATE_C1)
+			dev->safe_state = state;
 		state->enter = omap4_enter_idle;
 		sprintf(state->name, "C%d", count+1);
+		strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
 		count++;
 	}
 
-- 
1.6.0.4

[pm-core][PATCH v3 17/21] OMAP4: cpuidle: Switch to gptimer from twd in deeper C-states.

[Santosh Shilimkar]

CPU local timer(TWD) stops when the CPU is transitioning into
deeper C-States. Since these timers are not wakeup capable, we
need the wakeup capable global timer to program the wakeup time
depending on the next timer expiry.

It can be handled by registering a global wakeup capable timer along
with local timers marked with (mis)feature flag CLOCK_EVT_FEAT_C3STOP.
Then notify the clock events layer from idle code using
CLOCK_EVT_NOTIFY_BROADCAST_ENTER/EXIT).

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/cpuidle44xx.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 19a405c..daf41e1 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -12,6 +12,7 @@
 
 #include <linux/sched.h>
 #include <linux/cpuidle.h>
+#include <linux/clockchips.h>
 
 #include <asm/proc-fns.h>
 
@@ -85,6 +86,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
 	struct omap4_processor_cx *cx = cpuidle_get_statedata(state);
 	struct timespec ts_preidle, ts_postidle, ts_idle;
 	u32 cpu1_state;
+	int cpu_id = smp_processor_id();
 
 	/* Used to keep track of the total time in idle */
 	getnstimeofday(&ts_preidle);
@@ -111,8 +113,14 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
 	pwrdm_set_logic_retst(core_pd, cx->core_logic_state);
 	omap_set_pwrdm_state(core_pd, cx->core_state);
 
+	if (cx->type > OMAP4_STATE_C1)
+		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
+
 	omap4_enter_lowpower(dev->cpu, cx->cpu0_state);
 
+	if (cx->type > OMAP4_STATE_C1)
+		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+
 	getnstimeofday(&ts_postidle);
 	ts_idle = timespec_sub(ts_postidle, ts_preidle);
 
-- 
1.6.0.4

[pm-core][PATCH v3 18/21] OMAP4: cpuidle: Add CPU hotplug notifier and prepare() hook.

[Santosh Shilimkar]

On OMAP4 CPUidle, the low power states are triggered when CPU1
is offlined to OFF power state. When the CPU1 is online, no
low power states are supported.

The patch adds CPU hotplug notifier to manage the C-state
states using CPUidle prepare() hook and CPUIDLE_FLAG_IGNORE
c-state flag.

This was suggested by Kevin Hilman <khilman@ti.com> during
OMAP4 PM code review.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/cpuidle44xx.c |   64 +++++++++++++++++++++++++++++++++++++
 1 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index daf41e1..83b7f95 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -13,6 +13,8 @@
 #include <linux/sched.h>
 #include <linux/cpuidle.h>
 #include <linux/clockchips.h>
+#include <linux/notifier.h>
+#include <linux/cpu.h>
 
 #include <asm/proc-fns.h>
 
@@ -51,6 +53,8 @@ struct omap4_processor_cx {
 
 struct omap4_processor_cx omap4_power_states[OMAP4_MAX_STATES];
 static struct powerdomain *mpu_pd, *cpu1_pd, *core_pd;
+static int needs_state_data_update;
+static unsigned int state_flags = CPUIDLE_FLAG_IGNORE;
 
 /*
  * FIXME: Full latency numbers needs to be updated as part of
@@ -72,6 +76,31 @@ static struct cpuidle_params cpuidle_params_table[] = {
 };
 
 /**
+ * omap4_prepare_idle - Update C-state parameters dynamically
+ * @dev: cpuidle device
+ *
+ * Called from the CPUidle framework to prepare the device
+ * for idle before before calling the governor's select function.
+ */
+static int omap4_prepare_idle(struct cpuidle_device *dev)
+{
+	int i, ret = 0;
+
+	if (!needs_state_data_update)
+		return ret;
+
+	/*
+	 * Update the C-state flags based on CPU1 online
+	 * or offline state. On OMAP4, the low power C-states
+	 * are made available when only CPU1 is offline.
+	 */
+	for (i = OMAP4_STATE_C2; i < OMAP4_MAX_STATES; i++)
+		dev->states[i].flags = state_flags;
+
+	return ret;
+}
+
+/**
  * omap4_enter_idle - Programs OMAP4 to enter the specified state
  * @dev: cpuidle device
  * @state: The target state to be programmed
@@ -227,6 +256,36 @@ struct cpuidle_driver omap4_idle_driver = {
 	.owner =	THIS_MODULE,
 };
 
+/*
+ * CPU hotplug notifier to update the C-states when
+ * CPU1 is offline or onine. While updating C-state flag,
+ * keep the cpuidle disabled.
+ */
+static int __cpuinit omap_cpu_hotplug_notify(struct notifier_block *self,
+					 unsigned long action, void *unused)
+{
+	switch (action) {
+	case CPU_ONLINE:
+		disable_hlt();
+		needs_state_data_update = 1;
+		state_flags = CPUIDLE_FLAG_IGNORE;
+		enable_hlt();
+		break;
+	case CPU_DEAD:
+		disable_hlt();
+		needs_state_data_update = 1;
+		state_flags = CPUIDLE_FLAG_TIME_VALID;
+		enable_hlt();
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block __refdata omap_ilde_hotplug_notifier = {
+	.notifier_call = omap_cpu_hotplug_notify,
+};
+
 /**
  * omap4_idle_init - Init routine for OMAP4 idle
  *
@@ -272,12 +331,17 @@ int __init omap4_idle_init(void)
 	if (!count)
 		return -EINVAL;
 	dev->state_count = count;
+	dev->prepare = omap4_prepare_idle;
 
 	if (cpuidle_register_device(dev)) {
 		pr_err("%s: CPUidle register device failed\n", __func__);
 			return -EIO;
 		}
 
+	ret = register_hotcpu_notifier(&omap_ilde_hotplug_notifier);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 #else
-- 
1.6.0.4

[pm-core][PATCH v3 19/21] OMAP4: Remove un-used do_wfi() macro.

[Santosh Shilimkar]

With OMAP4 suspend, idle and hotplug series, we no longer need
do_wfi() macro.

Remove the same.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/include/mach/omap4-common.h |   10 ----------
 1 files changed, 0 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index a4b3beb..33fa3d3 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -16,16 +16,6 @@
 #include <asm/proc-fns.h>
 
 #ifndef __ASSEMBLER__
-/*
- * wfi used in low power code. Directly opcode is used instead
- * of instruction to avoid mulit-omap build break
- */
-#ifdef CONFIG_THUMB2_KERNEL
-#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
-#else
-#define do_wfi()			\
-		__asm__ __volatile__ (".word	0xe320f003" : : : "memory")
-#endif
 
 #ifdef CONFIG_CACHE_L2X0
 extern void __iomem *omap4_get_l2cache_base(void);
-- 
1.6.0.4

[pm-core][PATCH v3 20/21] OMAP4: PM: Set static dependency between MPUSS-EMIF and MPUSS-L3_1

[Santosh Shilimkar]

As per OMAP4430 TRM, the dynamic dependency between MPUSS<->MEMIF
and MPUSS<->L3_MAIN_1 clockdomains is enable by default. Refer
register CM_MPU_DYNAMICDEP description for details.

But it doesn't seems to work as expected and MPUSS doesn't wakeup
from off-mode if the static dependency is not set between
MPUSS<->EMIF and MPUSS<->L3_MAIN_1 clockdomains. At times, CPU
dead-locks with above static dependencies cleared.

The issue is under investigation with hardware team.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/pm44xx.c |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index b78417c..40a44a9 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -182,6 +182,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 static int __init omap4_pm_init(void)
 {
 	int ret;
+	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
 
 	if (!cpu_is_omap44xx())
 		return -ENODEV;
@@ -196,6 +197,35 @@ static int __init omap4_pm_init(void)
 
 	(void) clkdm_for_each(clkdms_setup, NULL);
 
+	/*
+	 * FIXME: Remove the MPUSS <-> EMIF static dependency once the
+	 * dynamic dependency issue is root-caused.
+	 * The dynamic dependency between MPUSS <-> MEMIF and MPUSS <-> L3_1
+	 * doesn't seems to work as expected and MPUSS does not wakeup
+	 * from off-mode if the static dependency is not set between them.
+	 * At times CPUs dead-locks with above static dependencies cleared.
+	 */
+	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
+	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
+	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
+	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm))
+		goto err2;
+
+	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
+	if (ret) {
+		pr_err("Failed to add MPUSS <-> EMIF wakeup dependency\n");
+		goto err2;
+	}
+
+	ret = clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
+	if (ret) {
+		pr_err("Failed to add MPUSS <-> L3_MAIN_1 wakeup dependency\n");
+		goto err2;
+	}
+
+	pr_info("OMAP4 PM: Temporary static dependency added between"
+		"MPUSS <-> EMIF and MPUSS <-> L3_MAIN_1.\n");
+
 	ret = omap4_mpuss_init();
 	if (ret) {
 		pr_err("Failed to initialise OMAP4 MPUSS\n");
-- 
1.6.0.4

[pm-core][PATCH v3 21/21] OMAP4: PM: Avoid omap4_pm_init() on OMAP4430 ES1.0

[Santosh Shilimkar]

On OMAP4430 ES1.0, Power Management features are not supported.
Avoid omap4_pm_init() on ES1.0 silicon so that we can continue
to use same kernel binary to boot on all OMAP4 silicons.

The ES1.0 boot failure with OMAP4 PM series was because of
the clockdomain initialisation code. Hardware supervised
clockdomain mode isn't functional for all clockdomains
on OMAP4430 ES1.0 silicon so avoid the same.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reported-by: Kevin Hilman <khilman@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/pm44xx.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 40a44a9..6de5267 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -187,6 +187,11 @@ static int __init omap4_pm_init(void)
 	if (!cpu_is_omap44xx())
 		return -ENODEV;
 
+	if (omap_rev() == OMAP4430_REV_ES1_0) {
+		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+		return -ENODEV;
+	}
+
 	pr_err("Power Management for TI OMAP4.\n");
 
 	ret = pwrdm_for_each(pwrdms_setup, NULL);
-- 
1.6.0.4