From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82F65C3DA4A for ; Thu, 1 Aug 2024 11:43:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=m2yqd1OqgjjZuyH37ODy/t4CJVCEOrVaVWOmJTBP89c=; b=a1nFgXVcVWNe8O7nvtr7CHjXlM FMY/upPsl16PQEh5voESLjADEZ6METHtD52gSvLgKYuxanE7zM9EHDzV+gs/XI/gg2Ojf1EbSRRKv pEVyQVn6nLeRdwoE5kMRb/2IRYNwGYJ5ToPctK4v/53Sfhz6NTN2dwZFNA8doL9hZK5ka7Mt48Py2 9Awh/RtOs24wR7ePQJKVTUpDGRe9OkTFllpWf5rQ+mp/PIM4sHPllDST1vDSjrQNcev3mwQN29fIq aAhAd9cZM3YaMSyEyy2gInBUQdIberpKTuXW7fxq4n7NiTs28vwf7FCQh8KnDC1h8Lxi/qJ9BEjJ8 ReT00GHA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZUDV-00000004xFP-2CSK; Thu, 01 Aug 2024 11:43:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZUD1-00000004x8y-1OwG for linux-arm-kernel@lists.infradead.org; Thu, 01 Aug 2024 11:43:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2968715A1; Thu, 1 Aug 2024 04:43:28 -0700 (PDT) Received: from [10.163.56.112] (unknown [10.163.56.112]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A36423F5A1; Thu, 1 Aug 2024 04:43:00 -0700 (PDT) Message-ID: <29466ee2-c769-493a-85b0-8821bfd83e4f@arm.com> Date: Thu, 1 Aug 2024 17:12:58 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64: cputype: Add Cortex-A725 definitions To: Mark Rutland , linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, james.morse@arm.com, will@kernel.org References: <20240801101803.1982459-1-mark.rutland@arm.com> <20240801101803.1982459-3-mark.rutland@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20240801101803.1982459-3-mark.rutland@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240801_044303_452461_07DF4B6C X-CRM114-Status: GOOD ( 13.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 8/1/24 15:48, Mark Rutland wrote: > Add cputype definitions for Cortex-A725. These will be used for errata > detection in subsequent patches. > > These values can be found in the Cortex-A725 TRM: > > https://developer.arm.com/documentation/107652/0001/ > > ... in table A-247 ("MIDR_EL1 bit descriptions"). > > Signed-off-by: Mark Rutland > Cc: Catalin Marinas > Cc: James Morse > Cc: Will Deacon > --- > arch/arm64/include/asm/cputype.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 5dc68ace305e5..5fd7caea44193 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -93,6 +93,7 @@ > #define ARM_CPU_PART_CORTEX_X4 0xD82 > #define ARM_CPU_PART_NEOVERSE_V3 0xD84 > #define ARM_CPU_PART_CORTEX_X925 0xD85 > +#define ARM_CPU_PART_CORTEX_A725 0xD87 > > #define APM_CPU_PART_XGENE 0x000 > #define APM_CPU_VAR_POTENZA 0x00 > @@ -173,6 +174,7 @@ > #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) > #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) > #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) > +#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) > #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) > #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) > #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) The CPU part number 0xD87 checks out in the mentioned document above. Reviewed-by: Anshuman Khandual