[PATCH 0/2] clk: sunxi-ng: d1: Fix halved MMC frequency

Andre Przywara
2025-02-26T11:03:38Z

Hi,

as Kuba reported, on an Allwinner T113-s3 based board the SD card
performance is only half of what we expect: ~11 MB/s instead of the
usual 23 MB/s.
Looking at our MMC mod clock definition, this seems to be due to a
missing fixed (and hidden) divider of 2, a "feature" of every other
Allwinner SoC from the last 10 years.

Patch 2/2 changes the MMC mod clock definition to carry this post_div
of 2, in line with the A64, H6, A100, and H616 SoCs.
Since the D1 clock driver describes clock parents using an array of
pointers, we need to use a new macro that allows both parent_data and
post_div to be specified. This is also needed by the new A523 clocks,
so I lifted the patch from there[1]. Chen-Yu reviewed that one already,
but I made some changes to make the macro more flexible, so I dropped
his tag.

I couldn't test this on a D1 board, so I'd be grateful if someone could
confirm that the SD card performance is now as expected. I simply used
"hdparm -t" to get a ballpark number of read performance, but any other
benchmark or even a timed file copy should do.

Thanks to Kuba for the report!

Cheers,
Andre

[1]
https://lore.kernel.org/linux-sunxi/20250214125359.5204-1-andre.przywara@arm.com/T/#m9adaa1fcea09185c561f3fd01ba895fa67af456c

Andre Przywara (2):
clk: sunxi-ng: mp: provide wrapper for setting feature flags
clk: sunxi-ng: d1: Add missing divider for MMC mod clocks

drivers/clk/sunxi-ng/ccu-sun20i-d1.c | 43 ++++++++++++++++------------
drivers/clk/sunxi-ng/ccu_mp.h | 19 ++++++++++--
2 files changed, 42 insertions(+), 20 deletions(-)

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2.25.1