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From: "CK Hu (胡俊光)" <ck.hu@mediatek.com>
To: "robh@kernel.org" <robh@kernel.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"Paul-pl Chen (陳柏霖)" <Paul-pl.Chen@mediatek.com>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>
Cc: "Sunny Shen (沈姍姍)" <Sunny.Shen@mediatek.com>,
	"Sirius Wang (王皓昱)" <Sirius.Wang@mediatek.com>,
	"Nancy Lin (林欣螢)" <Nancy.Lin@mediatek.com>,
	"Xiandong Wang (王先冬)" <Xiandong.Wang@mediatek.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"Jason-JH Lin (林睿祥)" <Jason-JH.Lin@mediatek.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"fshao@chromium.org" <fshao@chromium.org>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"Singo Chang (張興國)" <Singo.Chang@mediatek.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"treapking@chromium.org" <treapking@chromium.org>
Subject: Re: [PATCH v2 12/15] drm/mediatek: add OUTPROC support for MT8196
Date: Mon, 24 Mar 2025 09:00:01 +0000	[thread overview]
Message-ID: <297be0e3f2b5b9cb4d051cfae6e5f5868c3cb7b8.camel@mediatek.com> (raw)
In-Reply-To: <20250321093435.94835-13-paul-pl.chen@mediatek.com>

On Fri, 2025-03-21 at 17:33 +0800, paul-pl.chen wrote:
> From: Nancy Lin <nancy.lin@mediatek.com>
> 
> OUTPROC handles the post-stage of pixel processing in
> the overlapping procedure.OUTPROC manages pixels for
> gamma correction and ensures that pixel values are
> within the correct range.
> 
> Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
> Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com>
> ---

[snip]

> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_outproc.c b/drivers/gpu/drm/mediatek/mtk_disp_outproc.c
> new file mode 100644
> index 000000000000..a7c6d1982bca
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_outproc.c
> @@ -0,0 +1,242 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_framebuffer.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#include "mtk_crtc.h"
> +#include "mtk_ddp_comp.h"
> +#include "mtk_drm_drv.h"

Alphabetic order.

> +#include "mtk_disp_outproc.h"
> +
> +#define DISP_REG_OVL_OUTPROC_INTEN				0x004
> +#define OVL_OUTPROC_FME_CPL_INTEN					BIT(1)
> +#define DISP_REG_OVL_OUTPROC_INTSTA				0x008
> +#define DISP_REG_OVL_OUTPROC_DATAPATH_CON			0x010
> +#define OVL_OUTPROC_DATAPATH_CON_OUTPUT_CLAMP				BIT(26)
> +
> +#define DISP_REG_OVL_OUTPROC_EN					0x020
> +#define OVL_OUTPROC_OVL_EN						BIT(0)
> +#define DISP_REG_OVL_OUTPROC_RST				0x024
> +#define OVL_OUTPROC_RST							BIT(0)
> +#define DISP_REG_OVL_OUTPROC_SHADOW_CTRL			0x028
> +#define OVL_OUTPROC_BYPASS_SHADOW					BIT(2)
> +#define DISP_REG_OVL_OUTPROC_ROI_SIZE				0x030
> +
> +struct mtk_disp_outproc {
> +	void __iomem		*regs;
> +	struct clk		*clk;
> +	void			(*vblank_cb)(void *data);
> +	void			*vblank_cb_data;
> +	int			irq;
> +	struct cmdq_client_reg	cmdq_reg;
> +};
> +
> +void mtk_disp_outproc_register_vblank_cb(struct device *dev,
> +					 void (*vblank_cb)(void *),
> +					 void *vblank_cb_data)
> +{
> +	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
> +
> +	priv->vblank_cb = vblank_cb;
> +	priv->vblank_cb_data = vblank_cb_data;
> +}
> +
> +void mtk_disp_outproc_unregister_vblank_cb(struct device *dev)
> +{
> +	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
> +
> +	priv->vblank_cb = NULL;
> +	priv->vblank_cb_data = NULL;
> +}
> +
> +void mtk_disp_outproc_enable_vblank(struct device *dev)
> +{
> +	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
> +
> +	writel(OVL_OUTPROC_FME_CPL_INTEN, priv->regs + DISP_REG_OVL_OUTPROC_INTEN);
> +}
> +
> +void mtk_disp_outproc_disable_vblank(struct device *dev)
> +{
> +	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
> +
> +	writel(0x0, priv->regs + DISP_REG_OVL_OUTPROC_INTEN);
> +}
> +
> +static irqreturn_t mtk_disp_outproc_irq_handler(int irq, void *dev_id)
> +{
> +	struct mtk_disp_outproc *priv = dev_id;
> +	u32 val;
> +
> +	val = readl(priv->regs + DISP_REG_OVL_OUTPROC_INTSTA);
> +	if (!val)
> +		return IRQ_NONE;
> +
> +	writel(0x0, priv->regs + DISP_REG_OVL_OUTPROC_INTSTA);
> +
> +	if (priv->vblank_cb)
> +		priv->vblank_cb(priv->vblank_cb_data);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +void mtk_disp_outproc_config(struct device *dev, unsigned int w,
> +			     unsigned int h, unsigned int vrefresh,
> +			     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
> +
> +	dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> +
> +	//move mtk_ddp_write_mask to mtk_ddp_write

I think this comment is redundant.

> +	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_OVL_OUTPROC_ROI_SIZE);
> +	mtk_ddp_write_mask(cmdq_pkt, OVL_OUTPROC_DATAPATH_CON_OUTPUT_CLAMP,
> +			   &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_OUTPROC_DATAPATH_CON,
> +			   OVL_OUTPROC_DATAPATH_CON_OUTPUT_CLAMP);
> +}
> +
> +void mtk_disp_outproc_start(struct device *dev)
> +{
> +	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
> +	unsigned int tmp;
> +
> +	tmp = readl(priv->regs + DISP_REG_OVL_OUTPROC_SHADOW_CTRL);
> +	tmp = tmp | OVL_OUTPROC_BYPASS_SHADOW;
> +	writel(tmp, priv->regs + DISP_REG_OVL_OUTPROC_SHADOW_CTRL);
> +
> +	mtk_ddp_write(NULL, 0, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_OVL_OUTPROC_INTSTA);
> +	mtk_ddp_write_mask(NULL, OVL_OUTPROC_OVL_EN, &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_OUTPROC_EN, OVL_OUTPROC_OVL_EN);

Use readl() and writel().

> +}
> +
> +void mtk_disp_outproc_stop(struct device *dev)
> +{
> +	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
> +
> +	mtk_ddp_write_mask(NULL, 0, &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_OUTPROC_EN, OVL_OUTPROC_OVL_EN);
> +	mtk_ddp_write_mask(NULL, OVL_OUTPROC_RST, &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_OUTPROC_RST, OVL_OUTPROC_RST);
> +	mtk_ddp_write_mask(NULL, 0, &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_OUTPROC_RST, OVL_OUTPROC_RST);

Use readl() and writel().

> +}
> +
> +




  reply	other threads:[~2025-03-24  9:02 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-21  9:33 [PATCH v2 00/15] Add MediaTek SoC DRM support for MT8196 paul-pl.chen
2025-03-21  9:33 ` [PATCH v2 01/15] dt-bindings: arm: mediatek: mmsys: add compatible " paul-pl.chen
2025-03-24  9:33   ` Krzysztof Kozlowski
2025-03-21  9:33 ` [PATCH v2 02/15] dt-bindings: soc: mediatek: add mutex yaml " paul-pl.chen
2025-03-24  9:34   ` Krzysztof Kozlowski
2025-03-21  9:33 ` [PATCH v2 03/15] dt-bindings: display: mediatek: add EXDMA " paul-pl.chen
2025-03-24  2:45   ` CK Hu (胡俊光)
2025-05-14 16:25     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 04/15] dt-bindings: display: mediatek: add BLENDER " paul-pl.chen
2025-03-24  9:36   ` Krzysztof Kozlowski
2025-03-28  2:27     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 05/15] dt-bindings: display: mediatek: add OUTPROC " paul-pl.chen
2025-03-24 16:02   ` Rob Herring
2025-04-01 15:44     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 06/15] soc: mediatek: add mmsys support " paul-pl.chen
2025-03-24 17:09   ` AngeloGioacchino Del Regno
2025-04-02  4:06     ` Paul-pl Chen (陳柏霖)
2025-04-02  9:33       ` AngeloGioacchino Del Regno
2025-04-11  9:26         ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 07/15] soc: mediatek: mutex: refactor SOF settings for output components paul-pl.chen
2025-03-24 17:12   ` AngeloGioacchino Del Regno
2025-04-02  3:30     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 08/15] soc: mediatek: mutex: add mutex support for MT8196 paul-pl.chen
2025-03-21  9:33 ` [PATCH v2 09/15] drm/mediatek: Refine OVL format convert API and export to public paul-pl.chen
2025-03-25  2:57   ` CK Hu (胡俊光)
2025-05-13 16:22     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 10/15] drm/mediatek: add EXDMA support for MT8196 paul-pl.chen
2025-03-24  3:00   ` CK Hu (胡俊光)
2025-05-14 10:00     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 11/15] drm/mediatek: add BLENDER " paul-pl.chen
2025-03-24  8:33   ` CK Hu (胡俊光)
2025-05-13 17:12     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 12/15] drm/mediatek: add OUTPROC " paul-pl.chen
2025-03-24  9:00   ` CK Hu (胡俊光) [this message]
2025-03-28  2:57     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 13/15] drm/mediatek: add ovlsys_adaptor " paul-pl.chen
2025-04-11  3:07   ` CK Hu (胡俊光)
2025-05-14 16:18     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 14/15] drm/mediatek: Add support for multiple mmsys in the one mediatek-drm driver paul-pl.chen
2025-03-25  3:44   ` CK Hu (胡俊光)
2025-05-13 16:11     ` Paul-pl Chen (陳柏霖)
2025-03-21  9:33 ` [PATCH v2 15/15] drm/mediatek: Add support for MT8196 multiple mmsys paul-pl.chen

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