From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3 V2] CNS3xxx: Fix debug UART.
Date: Thu, 02 Oct 2014 16:39:45 +0200 [thread overview]
Message-ID: <2989906.dE3tTh8Pqq@wuerfel> (raw)
In-Reply-To: <m3oatzaqdz.fsf@t19.piap.pl>
On Monday 29 September 2014 08:32:08 Krzysztof Ha?asa wrote:
> UARTs on CNS3xxx are 8250-compatible, not AMBA.
> The base address for UART0 is 0x78000000 (physical)
> and 0xfb002000 (virtual).
>
> Signed-off-by: Krzysztof Ha?asa <khalasa@piap.pl>
I've applied it on next/soc now, as this seems to be an
important fix but it also interacts with other stuff we
have in next/soc already and I want to avoid conflicts.
One question though, just to make sure it's correct:
> @@ -1094,6 +1094,7 @@ config DEBUG_UART_PHYS
> + default 0x78000000 if DEBUG_CNS3XXX
> @@ -1155,6 +1155,7 @@ config DEBUG_UART_VIRT
> + default 0xfb002000 if DEBUG_CNS3XXX
It seems strange that the offset from the base address is
different for the VIRT and PHYS part. The early boot code
tries to map the registers using a supersection mapping,
which requires the same alignment within a 2MB area.
Do you know what is going on here?
Arnd
next prev parent reply other threads:[~2014-10-02 14:39 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-16 10:31 [PATCH 0/3] Fixes for CNS3xxx platform Krzysztof Hałasa
2014-09-16 10:35 ` [PATCH 1/3] CNS3xxx: Fix debug UART Krzysztof Hałasa
2014-09-16 10:36 ` [PATCH 2/3] CNS3xxx: Fix logical PCIe topology Krzysztof Hałasa
2014-09-16 10:37 ` [PATCH 3/3] CNS3xxx: Fix PCIe read size limit Krzysztof Hałasa
2014-09-25 21:43 ` [PATCH 0/3] Fixes for CNS3xxx platform Arnd Bergmann
2014-09-29 6:26 ` Krzysztof Hałasa
2014-09-29 6:34 ` Krzysztof Hałasa
2014-09-29 6:32 ` [PATCH 1/3 V2] CNS3xxx: Fix debug UART Krzysztof Hałasa
2014-10-02 14:39 ` Arnd Bergmann [this message]
2014-10-03 10:22 ` Krzysztof Hałasa
2014-10-03 14:23 ` Arnd Bergmann
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