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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE4MDA4NyBTYWx0ZWRfX7yITxqb9ttPN biO9bjOTQFCDYICJvwZNefo8zxgxdnUpF+2sdFIdHF9ySQK2dbPrwVdEedM/H691Mq4gOByHw+L BI5h8Dbc5b9V2gSqlxI40sHqjOUjjKFSAgz7p2CBjzwDJaqQj4Vv1O92LMYbs7CVFI4QHalsTnk Ek3TL6/zvsBB1/PTIRSIyKWed/ftunWX1frHPlbWJ50sNcKgca9CAZEXTNidZTpncIPIQSvE4du rXJBtrtnzlnJCeaSPPk0YtaefrJH7Q4IsSFe3FbJI9L1+l0okgLXam+qxORs9yr7XhRAFjgEm/F eFD30dqHChf5iLaG4SwNZ6yXQkV/pI93Hqy4kBrmRj/QuX2/ONi0AeZYiBcJbcG1EWj1qcY7YBw tdM9U0SwSgjmiuwJgyQH+twPQqDH4K9ONW7KXGtj3TMhycCscpHLGmT8/ahSwBmulpEIUj6SeaV pPujtroqFrUFWewIeXQ== X-Proofpoint-GUID: h_hk7xl13SfGagY_SwFZwX89z9u34Yrf X-Proofpoint-ORIG-GUID: h_hk7xl13SfGagY_SwFZwX89z9u34Yrf X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE4MDA4NyBTYWx0ZWRfX4Tkj/tKVWX8+ dyDFhrWTPdSSR6T+nqKdA55wFw4naGvb28ScidP2dCnUpDnp9qNratjQ4CIel/VLMQ91kNLsd17 Niu7hv6uDaGWEKMRAPLgHsuHj7COwJY= X-Authority-Analysis: v=2.4 cv=YrI/gYYX c=1 sm=1 tr=0 ts=6a33ba57 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=gDzzPNA0uyMDLQwxZz4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-18_01,2026-06-17_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606180087 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260618_022856_625577_068DBBDF X-CRM114-Status: GOOD ( 26.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/17/26 4:26 PM, Bibek Kumar Patro wrote: > > > On 6/16/2026 5:51 AM, Dmitry Baryshkov wrote: >> On Mon, Jun 15, 2026 at 06:36:51PM +0530, Bibek Kumar Patro wrote: >>> >>> >>> On 6/8/2026 7:25 PM, Dmitry Baryshkov wrote: >>>> On Tue, May 26, 2026 at 08:12:03PM +0530, Bibek Kumar Patro wrote: >>>>> On some SoCs the SMMU registers require an active interconnect >>>>> bandwidth vote to be accessible. While other clients typically >>>>> satisfy this requirement implicitly, certain corner cases (e.g. >>>>> during sleep/wakeup transitions) can leave the SMMU without a >>>>> vote, causing intermittent register access failures. >>>>> >>>>> Add support for an optional interconnect path to the arm-smmu >>>>> driver and vote for bandwidth while the SMMU is active. The path >>>>> is acquired from DT if present and ignored otherwise. >>>>> >>>>> The bandwidth vote is enabled before accessing SMMU registers >>>>> during probe and runtime resume, and released during runtime >>>>> suspend and on error paths. >>>>> >>>>> Generally, from an architectural perspective, GEM_NOC and DDR are >>>>> expected to have an active vote whenever the adreno_smmu block is >>>>> powered on. In most common use cases, this requirement is implicitly >>>>> satisfied because other GPU-related clients (for example, the GMU >>>>> device) already hold a GEM_NOC vote when adreno_smmu is enabled. >>>>> >>>>> However, there are certain corner cases, such as during sleep/wakeup >>>>> transitions, where the GEM_NOC vote can be removed before adreno_smmu >>>>> is powered down. If adreno_smmu is then accessed while the interconnect >>>>> vote is missing, it can lead to the observed failures. Because of the >>>>> precise ordering involved, this scenario is difficult to reproduce >>>>> consistently. >>>>> (also GDSC is involved in adreno usecases can have an independent vote) >>>>> >>>>> Signed-off-by: Bibek Kumar Patro >>>>> --- >>>>>    drivers/iommu/arm/arm-smmu/arm-smmu.c | 57 +++++++++++++++++++++++++++++++++-- >>>>>    drivers/iommu/arm/arm-smmu/arm-smmu.h |  2 ++ >>>>>    2 files changed, 57 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c >>>>> index 0bd21d206eb3e75c3b9fb1364cdc92e82c5aa499..07c7e44ec6a5bd1488f00f87d859a20495e46601 100644 >>>>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c >>>>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c >>>>> @@ -53,6 +53,11 @@ >>>>>    #define MSI_IOVA_BASE            0x8000000 >>>>>    #define MSI_IOVA_LENGTH            0x100000 >>>>> +/* Interconnect bandwidth vote values for the SMMU register access path */ >>>>> +#define ARM_SMMU_ICC_AVG_BW        0 >>>>> +#define ARM_SMMU_ICC_PEAK_BW_HIGH    1000 >>>> >>>> totally random numbers, which might be different for non-Qualcomm platform. >>>> >>> >>> Ideally, any non-zero value would be enough to keep the path active. >> >> This is true for Qualcomm devices. However, you are adding this to a >> generic code. >> >>> Here 1 Would be enough to keep the path active, but might be too small to >>> reliably keep the bus active. >>> Other is UINT_MAX, which will reliably keep the bus active but might cause a >>> power penalty. >>> >>> #define ARM_SMMU_ICC_PEAK_BW_HIGH    UINT_MAX >>> >>> seems to be suitable here to reliably keep the bus active by BCM >>> for both Qualcomm and non-Qualcomm platforms (with some power penalty). >>> >>> LMK, if you feel otherwise. >> >> Shift it to the qcom instance or provide platform-specific values? (My >> preference would be towards the first solution). >> > > > To support platform-specific values, we may need to introduce a LUT-based approach in the driver. (Bandwidth voting values cannot be placed in device-tree property IIRC ?) > > Currently, all Qualcomm platforms use 0x1000 for SMMU ICC voting. I (you used decimal 1000) > can evaluate if this could be moved to a Qualcomm-specific > implementation. Add a vendor hook to arm_smmu_runtime_suspend/resume and handle it within the QC driver Konrad