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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id n20-20020a7bc5d4000000b003fe2a40d287sm1413364wmk.1.2023.08.10.01.35.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Aug 2023 01:35:43 -0700 (PDT) Message-ID: <2a751a64-559e-cb17-4359-7f368c1b42ca@redhat.com> Date: Thu, 10 Aug 2023 10:35:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v3 23/27] KVM: arm64: nv: Add SVC trap forwarding To: Marc Zyngier , kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Mark Brown , Mark Rutland , Will Deacon , Alexandru Elisei , Andre Przywara , Chase Conklin , Ganapatrao Kulkarni , Darren Hart , Miguel Luis , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu References: <20230808114711.2013842-1-maz@kernel.org> <20230808114711.2013842-24-maz@kernel.org> From: Eric Auger In-Reply-To: <20230808114711.2013842-24-maz@kernel.org> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230810_013549_328131_1122A57C X-CRM114-Status: GOOD ( 19.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 8/8/23 13:47, Marc Zyngier wrote: > HFGITR_EL2 allows the trap of SVC instructions to EL2. Allow these > traps to be forwarded. Take this opportunity to deny any 32bit activity > when NV is enabled. I can't figure out how HFGITR_EL2.{SVC_EL1, SVC_EL0 and ERET} are handled. Please could you explain. Eric > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/arm.c | 4 ++++ > arch/arm64/kvm/handle_exit.c | 12 ++++++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > index 72dc53a75d1c..8b51570a76f8 100644 > --- a/arch/arm64/kvm/arm.c > +++ b/arch/arm64/kvm/arm.c > @@ -36,6 +36,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -818,6 +819,9 @@ static bool vcpu_mode_is_bad_32bit(struct kvm_vcpu *vcpu) > if (likely(!vcpu_mode_is_32bit(vcpu))) > return false; > > + if (vcpu_has_nv(vcpu)) > + return true; > + > return !kvm_supports_32bit_el0(); > } > > diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c > index 6dcd6604b6bc..3b86d534b995 100644 > --- a/arch/arm64/kvm/handle_exit.c > +++ b/arch/arm64/kvm/handle_exit.c > @@ -226,6 +226,17 @@ static int kvm_handle_eret(struct kvm_vcpu *vcpu) > return 1; > } > > +static int handle_svc(struct kvm_vcpu *vcpu) > +{ > + /* > + * So far, SVC traps only for NV via HFGITR_EL2. A SVC from a > + * 32bit guest would be caught by vpcu_mode_is_bad_32bit(), so > + * we should only have to deal with a 64 bit exception. > + */ > + kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); > + return 1; > +} > + > static exit_handle_fn arm_exit_handlers[] = { > [0 ... ESR_ELx_EC_MAX] = kvm_handle_unknown_ec, > [ESR_ELx_EC_WFx] = kvm_handle_wfx, > @@ -239,6 +250,7 @@ static exit_handle_fn arm_exit_handlers[] = { > [ESR_ELx_EC_SMC32] = handle_smc, > [ESR_ELx_EC_HVC64] = handle_hvc, > [ESR_ELx_EC_SMC64] = handle_smc, > + [ESR_ELx_EC_SVC64] = handle_svc, > [ESR_ELx_EC_SYS64] = kvm_handle_sys_reg, > [ESR_ELx_EC_SVE] = handle_sve, > [ESR_ELx_EC_ERET] = kvm_handle_eret, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel