From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCAF6C43461 for ; Wed, 9 Sep 2020 06:40:34 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5C9812068D for ; Wed, 9 Sep 2020 06:40:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="iwuzI2XU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5C9812068D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:References: To:Subject:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ao75b5yKK2A4RRJ15jlLroBG0hK1BgzvlAiWvNXCHzY=; b=iwuzI2XUqTbLY9WYZKJ+Z7rba 1vRs2rKGbGP2zLgHYcEvjAKspb2BqB3PUjrAnpeBzNXfSoUiHNZs/awFhfLIT7x0dWVjKXjbR0phn 2g/2EDSMUwRZG3HDLqagWnPdVJzVMKJ3t1Fk3ujHcuVY8w3t36zjgYR5E6ETLUVPZ2eVsuJ/6i3r1 p/VRQ1axywYcPccYiYt8ENkfYMTUJkSA1/4Lt6UQ2izhkxrId4WfvdjOyM6PRKMYMmtDAKHKRSw6O qRiOiRgpGfYTepU4EKpI2crdxtGovHCFHeqQ+Cq3SXLe+LYwTnn9uwcnWTnfk5of/fDpKGlL3Ukw/ uymbe1R2A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFtl9-0006ik-B3; Wed, 09 Sep 2020 06:39:11 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFtl6-0006hs-9Y for linux-arm-kernel@lists.infradead.org; Wed, 09 Sep 2020 06:39:09 +0000 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 3EE38DF2CF89AAF3B22E; Wed, 9 Sep 2020 14:39:05 +0800 (CST) Received: from [10.67.76.227] (10.67.76.227) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Wed, 9 Sep 2020 14:38:59 +0800 From: Jonathan Zhou Subject: Re: [PATCH v2] Coresight: etm4x: add support for Self-hosted trace To: Will Deacon , References: <1598860966-70616-1-git-send-email-jonathan.zhouwen@huawei.com> <20200907210050.GA13815@willie-the-truck> Message-ID: <2ab9f4e1-dbb6-38d8-a7a3-0728c8d189c4@huawei.com> Date: Wed, 9 Sep 2020 14:38:59 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.2.1 MIME-Version: 1.0 In-Reply-To: <20200907210050.GA13815@willie-the-truck> Content-Language: en-GB X-Originating-IP: [10.67.76.227] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200909_023908_808588_178C4B21 X-CRM114-Status: GOOD ( 21.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shaokun Zhang , Catalin Marinas , linux-arm-kernel@lists.infradead.org, Suzuki K Poulose Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will Thanks for your review and thanks for adding Mathieu. On 08/09/2020 05:00, Will Deacon wrote: > [+ Mathieu, since he maintains the driver you're changing] > > On Mon, Aug 31, 2020 at 04:02:46PM +0800, Jonathan Zhou wrote: >> ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4 >> Self-hosted Trace Extensions. It provides control of exception >> levels and security states. Let's add this feature detection and >> enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is >> supported. >> >> Cc: Catalin Marinas >> Cc: Will Deacon >> Cc: Suzuki K Poulose >> Cc: Shaokun Zhang >> Signed-off-by: Jonathan Zhou >> --- >> arch/arm64/include/asm/sysreg.h | 8 ++++++++ >> drivers/hwtracing/coresight/coresight-etm4x.c | 23 +++++++++++++++++++++++ >> 2 files changed, 31 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index 554a7e8ecb07..53da5f326667 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -184,6 +184,13 @@ >> >> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) >> >> +/* Trace Filter control */ >> +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) >> +/* Trace is allowed at EL0 */ >> +#define SYS_TRFCR_EL1_E0TRE BIT(0) >> +/* Trace is allowed at EL1 */ >> +#define SYS_TRFCR_EL1_E1TRE BIT(1) > > Do we also need to make sure we initialise TRFCR_EL2 correctly for the host? > As Suziki said in the previous patch[1], accessing TRFCR_EL1 under EL2 will be routed to TRFCR_EL2. I just did a default config in this patch. Actually, it should be better if we can do this based on the trace sessions or the kernel config. [1] https://www.spinics.net/lists/arm-kernel/msg818953.html Regards Jonathan > Will > > (keeping rest of the patch intact for Mathieu) > >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c >> index 96425e818fc2..f72b457c2bad 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c >> @@ -28,6 +28,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info) >> CS_LOCK(drvdata->base); >> } >> >> +static void etm4_init_sysctrl(void *info) >> +{ >> + u64 sys_trfcr_el1, dfr0; >> + int trace_filt; >> + >> + dfr0 = read_sysreg(id_aa64dfr0_el1); >> + >> + trace_filt = cpuid_feature_extract_unsigned_field(dfr0, >> + ID_AA64DFR0_SELF_HOSTED_SHIFT); >> + /* if selfhosted trace implemented, enable trace EL0 as default. */ >> + if (trace_filt == 0x1) { >> + sys_trfcr_el1 = read_sysreg_s(SYS_TRFCR_EL1); >> + write_sysreg_s(sys_trfcr_el1 | SYS_TRFCR_EL1_E0TRE, >> + SYS_TRFCR_EL1); >> + isb(); >> + } >> +} >> + >> static void etm4_set_default_config(struct etmv4_config *config) >> { >> /* disable all events tracing */ >> @@ -1504,6 +1523,10 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) >> etm4_init_arch_data, drvdata, 1)) >> dev_err(dev, "ETM arch init failed\n"); >> >> + if (smp_call_function_single(drvdata->cpu, >> + etm4_init_sysctrl, drvdata, 1)) >> + dev_err(dev, "ETM sysctrl init failed\n"); >> + >> ret = etm4_pm_setup_cpuslocked(); >> cpus_read_unlock(); >> >> -- >> 1.9.1 >> > . > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel