From: yixun.lan@amlogic.com (Yixun Lan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA
Date: Mon, 6 Nov 2017 17:51:02 +0800 [thread overview]
Message-ID: <2b3a9136-4bec-00a3-85e3-09c69d2dffc1@amlogic.com> (raw)
In-Reply-To: <1509959454.1328.8.camel@baylibre.com>
Hi Jerome:
On 11/06/17 17:10, Jerome Brunet wrote:
> On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote:
>> According to the datasheet, in Meson-GXBB/GXL series,
>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
>> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>>
>> Test passed at gxl_skt dev board.
> I think this refer to a board naming used in amlogic vendor kernel ?
> Would you mind telling what it is ?
>
sorry, it's actually tested at gxl-s905x-p212 board.
prev parent reply other threads:[~2017-11-06 9:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-06 7:52 [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA Yixun Lan
2017-11-06 8:57 ` Neil Armstrong
2017-11-06 9:31 ` Yixun Lan
2017-11-06 22:03 ` Martin Blumenstingl
2017-11-07 5:44 ` Yixun Lan
2017-11-06 9:10 ` Jerome Brunet
2017-11-06 9:38 ` Yixun Lan
2017-11-06 9:44 ` Jerome Brunet
2017-11-06 9:45 ` Jerome Brunet
2017-11-06 9:51 ` Yixun Lan [this message]
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