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Fri, 15 Nov 2024 09:29:48 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5632340053; Fri, 15 Nov 2024 09:28:22 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 31155263566; Fri, 15 Nov 2024 09:27:14 +0100 (CET) Received: from [10.129.178.212] (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Fri, 15 Nov 2024 09:27:13 +0100 Message-ID: <2b52093a-103f-4dd4-bb6d-c04dc9f68e98@foss.st.com> Date: Fri, 15 Nov 2024 09:27:05 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] dt-bindings: PCI: Add STM32MP25 PCIe root complex bindings To: Bjorn Helgaas CC: , , , , , , , , , , , , , , , , , References: <20241112182809.GA1853254@bhelgaas> Content-Language: en-US From: Christian Bruel In-Reply-To: <20241112182809.GA1853254@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.129.178.212] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241115_003009_702693_EECB5978 X-CRM114-Status: GOOD ( 13.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/12/24 19:28, Bjorn Helgaas wrote: > On Tue, Nov 12, 2024 at 05:19:21PM +0100, Christian Bruel wrote: >> Document the bindings for STM32MP25 PCIe Controller configured in >> root complex mode. >> Supports 4 legacy interrupts and MSI interrupts from the ARM >> GICv2m controller. >> >> Allow tuning to change payload (default 128B) thanks to the >> st,max-payload-size entry. >> Can also limit the Maximum Read Request Size on downstream devices to the >> minimum possible value between 128B and 256B. >> >> STM32 PCIE may be in a power domain which is the case for the STM32MP25 >> based boards. >> Supports wake# from wake-gpios > >> + st,limit-mrrs: >> + description: If present limit downstream MRRS to 256B >> + type: boolean >> + >> + st,max-payload-size: >> + description: Maximum Payload size to use >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [128, 256] >> + default: 128 > > MRRS and MPS are not specific to this device. Not sure why you need > them, but if you do need them, I think they should be generic. Agree. On a second thought, this was to fix an old errata and can be dropped now, as well as the associated quirks. Will re-post as generic if needed later on thanks, Christian