From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDF3FD2E015 for ; Wed, 23 Oct 2024 05:50:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=91Wk150n2+rrQ/BUHOiWBIldWJPl7rxdhOf5L+f4tLg=; b=MVojuKW13vopEsdg1uuqv4kfZr zz85AHkrwkQOl7+z56jJJZ5P8HWzkitgyNHNbG2g0dRcorJwQIyJYIb9kt3suD/YOyGZ+/D9SSwp+ sydCU/2/SIceAmQ6lUb1hhGmR1OFVkvqxAlu/K+BvNaQdIKYsoLc/hawdxIKIWGKOxcb02SMJxVGd atuPjrjPnB3esT6Mtp8GMGOvu64J9WpbsINtQPMexxtjGuKQ0U1XzVAN3oJh8Zxlq4Rypjr/YY67d gGOh2hUIbi21FOyBu61DtDCTkHEeSHI1dI5cxX756jYDkTmF6+3z7JNzX4zDi8Kds1JvSDyOWUwv1 Goa5C/dQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t3UGX-0000000D6jR-3u67; Wed, 23 Oct 2024 05:50:41 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t3UEH-0000000D6Cm-3nzy for linux-arm-kernel@lists.infradead.org; Wed, 23 Oct 2024 05:48:23 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EAED7339; Tue, 22 Oct 2024 22:48:47 -0700 (PDT) Received: from [10.163.41.228] (unknown [10.163.41.228]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 42C003F528; Tue, 22 Oct 2024 22:48:13 -0700 (PDT) Message-ID: <2c51de68-fcca-4457-b8e9-b488d8030738@arm.com> Date: Wed, 23 Oct 2024 11:18:12 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register To: Mark Rutland Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev References: <20241001043602.1116991-1-anshuman.khandual@arm.com> <20241001043602.1116991-2-anshuman.khandual@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241022_224822_070406_83074305 X-CRM114-Status: GOOD ( 20.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/22/24 21:26, Mark Rutland wrote: > On Tue, Oct 01, 2024 at 10:06:00AM +0530, Anshuman Khandual wrote: >> This adds required field details for ID_AA64DFR1_EL1, and also drops dummy >> ftr_raz[] array which is now redundant. These register fields will be used >> to enable increased breakpoint and watchpoint registers via FEAT_Debugv8p9 >> later. >> >> Cc: Catalin Marinas >> Cc: Will Deacon >> cc: Mark Brown >> Cc: Mark Rutland >> Cc: Marc Zyngier >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Anshuman Khandual >> --- >> arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++----- >> 1 file changed, 16 insertions(+), 5 deletions(-) >> >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 718728a85430..bd4d85f5dd92 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -530,6 +530,21 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { >> ARM64_FTR_END, >> }; >> >> +static const struct arm64_ftr_bits ftr_id_aa64dfr1[] = { >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ABL_CMPs_SHIFT, 8, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_DPFZS_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_EBEP_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ITE_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ABLE_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_PMICNTR_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SPMU_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_CTX_CMPs_SHIFT, 8, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_WRPs_SHIFT, 8, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_BRPs_SHIFT, 8, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SYSPMUID_SHIFT, 8, 0), >> + ARM64_FTR_END, >> +}; >> + > > Is there some general principle that has been applied here? e.g. is this > STRICT unless we know of variation in practice? Yes, that's correct. STRICT unless there is a known variation in practice. > > e.g. it seems a bit odd that ABLE cannot vary while the number of > breakpoints can... But all these (ABL_CMPs, CTX_CMPs, WRPs, BRPs) are marked as FTR_NONSTRICT. Would not that allow ABL_CMPs to vary as well ? Although the existing break-point numbers are currently marked FTR_STRICT, should they be changed first ? static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { ................... ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), ................... } > > I suspect we will see systems with mismatched EBEP too, but maybe I'm > wrong. Should that be marked FTR_NONSTRICT as well ? But is there a definite way to confirm if systems could/might come up with such variations in features between different cpus ? > > Mark. > >> static const struct arm64_ftr_bits ftr_mvfr0[] = { >> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), >> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), >> @@ -708,10 +723,6 @@ static const struct arm64_ftr_bits ftr_single32[] = { >> ARM64_FTR_END, >> }; >> >> -static const struct arm64_ftr_bits ftr_raz[] = { >> - ARM64_FTR_END, >> -}; >> - >> #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ >> .sys_id = id, \ >> .reg = &(struct arm64_ftr_reg){ \ >> @@ -784,7 +795,7 @@ static const struct __ftr_reg_entry { >> >> /* Op1 = 0, CRn = 0, CRm = 5 */ >> ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), >> - ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), >> + ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_id_aa64dfr1), >> >> /* Op1 = 0, CRn = 0, CRm = 6 */ >> ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), >> -- >> 2.25.1 >>