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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=louisalexis.eyraud@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1788426249; s=zohomail; d=collabora.com; i=louisalexis.eyraud@collabora.com; h=Message-ID:Subject:Subject:From:From:To:To:Cc:Cc:Date:Date:In-Reply-To:Content-Type:Content-Transfer-Encoding:MIME-Version:Message-Id:Reply-To; bh=aECgqs6JZ6BZsxQ6mCtynd9VQxvrPgGlkCeCbvLdpQI=; b=NtirWF7a0Cc0Lh1qAbupCDbyhSss1cFAHIGDmN0w2pFsGHTLTRxCQLcjd8cF/n49 AwqVpUMcmweeNyTf/wqZ5uswcM7EsKaJPczjzMFptgivpiGlKEfz91y2BaKcD8Lw2Aq ui55znASyqR06/I+Tw4rIw5k94afctSVbMdBECAI= Received: by mx.zohomail.com with SMTPS id 1788426248393643.0972373499999; Thu, 3 Sep 2026 02:04:08 -0700 (PDT) Message-ID: <2c8405eac9e72409154c98bb31b3fbed10be5755.camel@collabora.com> Subject: Re: [PATCH] drm/mediatek: mtk_hdmi_v2: fix VID_DOWNSAMPLE_CONFIG register offset From: Louis-Alexis Eyraud To: Julien Stephan , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tommy Chen Date: Thu, 03 Sep 2026 11:04:03 +0200 In-Reply-To: <20260828-mtk-hdmi-v2-fix-register-offset-v1-1-118ad5d7ebe3@baylibre.com> References: <20260828-mtk-hdmi-v2-fix-register-offset-v1-1-118ad5d7ebe3@baylibre.com> Organization: Collabora Ltd Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.60.2 (3.60.2-1.fc44) MIME-Version: 1.0 X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260903_020413_147563_3DB9E8F9 X-CRM114-Status: GOOD ( 10.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Julien, On Fri, 2026-08-28 at 14:10 +0200, Julien Stephan wrote: > According to the datasheet, VID_DOWNSAMPLE_CONFIG is at offset 0x8f0; > 0x8d0 is the VID_CSC_COEFF_0 register. >=20 > Fixes: 8d0f79886273 ("drm/mediatek: Introduce HDMI/DDC v2 for > MT8195/MT8188") > Signed-off-by: Julien Stephan > --- > =C2=A0drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h | 2 +- > =C2=A01 file changed, 1 insertion(+), 1 deletion(-) >=20 >=20 I've checked in the MT8370, MT8390 (MT8188 variants) and MT8395 (MT8195 variants) datasheets and 0x8f0 offset is indeed the correct one. So, Reviewed-by: Louis-Alexis Eyraud Regards, Louis-Alexis